LH79520 查看數據表（PDF） - NXP Semiconductors.
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LH79520 Datasheet PDF : 59 Pages
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LH79520
NXP Semiconductors
System-on-Chip
Table 2. LH79520 Signal Descriptions (Cont’d)
PIN NO. SIGNAL NAME
52 PG7
53 PG6
54 PG5
56 PG4
57 PG3
58 PG2
59 PG1
60 PG0
34 PH7
35 PH6
41 PH5
42 PH4
43 PH3
44 PH2
50 PH1
51 PH0
145 CTOUT1B
96 nRESETIN
97 nRESETOUT
114 INT7
115 INT6
144 INT5
150 INT4
151 INT3
152 INT2
153 INT1
155 INT0
93 XTALIN
94 XTALOUT
89 XTAL32IN
90 XTAL32OUT
88 CLKINSEL
98 CLKIN
99 CLKEN
156 CLKOUT
98 UARTCLK
174 nTRST
170 TMS
173 TCLK
172 TDI
171 TDO
175 TEST1
176 TEST2
1
nTSTA
TYPE
DESCRIPTION
Input/Output General Purpose I/O Signals - Port G
Input/Output General Purpose I/O Signals - Port H
COUNTER/TIMER (C/T)
Output Counter/Timer Output
RESET, CLOCK, AND POWER CONTROLLER (RCPC)
Input
Reset Input
Output Reset Output
Input
External Interrupt Input
Input
External Interrupt Input
Input
External Interrupt Input
Input
External Interrupt Input
Input
External Interrupt Input
Input
External Interrupt Input
Input
External Interrupt Input
Input
External Interrupt Input
Input
Crystal Input
Output Crystal Output
Input
32.768 kHz Crystal Oscillator Input
Output 32.768 kHz Crystal Oscillator Output
Input
External Clock Select
Input
External Clock Input (if CLKINSEL = HIGH at reset)
Output
External Clock Enable
(if CLKINSEL = LOW at reset, then this pin functions as PF1)
Output Clock Out (selectable from the internal bus clock or 32.768)
Input
External UART Clock Input (with CLKSEL = LOW)
TEST INTERFACE
Input
JTAG Test Reset Input
Input
JTAG Test Mode Select Input
Input
JTAG Test Clock Input
Input
JTAG Test Serial Data Input
Output JTAG Test Data Serial Output
Input
Tie LOW for Normal Operation (has internal pull-down).
Input
JTAG Debug Enable: Tie LOW for Normal Operation; pull HIGH to
enable JTAG Debugging (has internal pull-down).
Input
Tie HIGH for Normal Operation (has internal pull-up).
NOTES
1
1
1
1
1
1, 3
1
1
1
1
1
1
1
1
1
8
Rev. 01 — 16 July 2007
Preliminary data sheet
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