LM3S601 查看數據表（PDF） - Unspecified

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LM3S601

Microcontroller

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LM3S601 Microcontroller

Table of Contents

About This Document .................................................................................................................... 18

Audience .............................................................................................................................................. 18

About This Manual ................................................................................................................................ 18

Related Documents ............................................................................................................................... 18

Documentation Conventions .................................................................................................................. 18

1

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.4.9

Architectural Overview ...................................................................................................... 20

Product Features ...................................................................................................................... 20

Target Applications .................................................................................................................... 25

High-Level Block Diagram ......................................................................................................... 25

Functional Overview .................................................................................................................. 26

ARM Cortex™-M3 ..................................................................................................................... 27

Motor Control Peripherals .......................................................................................................... 27

Analog Peripherals .................................................................................................................... 28

Serial Communications Peripherals ............................................................................................ 29

System Peripherals ................................................................................................................... 30

Memory Peripherals .................................................................................................................. 30

Additional Features ................................................................................................................... 31

Hardware Details ...................................................................................................................... 32

System Block Diagram .............................................................................................................. 33

2

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 34

Block Diagram .......................................................................................................................... 35

Functional Description ............................................................................................................... 35

Serial Wire and JTAG Debug ..................................................................................................... 35

Embedded Trace Macrocell (ETM) ............................................................................................. 36

Trace Port Interface Unit (TPIU) ................................................................................................. 36

ROM Table ............................................................................................................................... 36

Memory Protection Unit (MPU) ................................................................................................... 36

Nested Vectored Interrupt Controller (NVIC) ................................................................................ 36

3

Memory Map ....................................................................................................................... 40

4

Interrupts ............................................................................................................................ 42

5

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

JTAG Interface .................................................................................................................... 44

Block Diagram .......................................................................................................................... 45

Functional Description ............................................................................................................... 45

JTAG Interface Pins .................................................................................................................. 46

JTAG TAP Controller ................................................................................................................. 47

Shift Registers .......................................................................................................................... 48

Operational Considerations ........................................................................................................ 48

Initialization and Configuration ................................................................................................... 49

Register Descriptions ................................................................................................................ 50

Instruction Register (IR) ............................................................................................................. 50

Data Registers .......................................................................................................................... 52

6

6.1

6.1.1

System Control ................................................................................................................... 54

Functional Description ............................................................................................................... 54

Device Identification .................................................................................................................. 54

October 01, 2007

3

Preliminary

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