LM3S817-IQC25-A0T 查看數據表（PDF） - Unspecified
零件编号
产品描述 (功能)
生产厂家
LM3S817-IQC25-A0T Datasheet PDF : 379 Pages
| |||
LM3S817 Data Sheet
10. Watchdog Timer ................................................................................................................ 185
10.1 Block Diagram ................................................................................................................................... 185
10.2 Functional Description ....................................................................................................................... 186
10.3 Initialization and Configuration........................................................................................................... 186
10.4 Register Map ..................................................................................................................................... 186
10.5 Register Descriptions......................................................................................................................... 187
11. Analog-to-Digital Converter (ADC) .................................................................................. 208
11.1 Block Diagram ................................................................................................................................... 209
11.2 Functional Description ....................................................................................................................... 209
11.2.1 Sample Sequencers .......................................................................................................................... 209
11.2.2 Module Control .................................................................................................................................. 210
11.2.3 Hardware Sample Averaging Circuit.................................................................................................. 211
11.2.4 Analog-to-Digital Converter ............................................................................................................... 211
11.2.5 Test Modes ........................................................................................................................................ 211
11.2.6 Internal Temperature Sensor ............................................................................................................. 211
11.3 Initialization and Configuration........................................................................................................... 211
11.3.1 Module Initialization ........................................................................................................................... 212
11.3.2 Sample Sequencer Configuration ...................................................................................................... 212
11.4 Register Map ..................................................................................................................................... 212
11.5 Register Descriptions......................................................................................................................... 213
12. Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 238
12.1 Block Diagram ................................................................................................................................... 239
12.2 Functional Description ....................................................................................................................... 239
12.2.1 Transmit/Receive Logic ..................................................................................................................... 239
12.2.2 Baud-Rate Generation ....................................................................................................................... 240
12.2.3 Data Transmission ............................................................................................................................. 241
12.2.4 FIFO Operation .................................................................................................................................. 241
12.2.5 Interrupts............................................................................................................................................ 241
12.2.6 Loopback Operation .......................................................................................................................... 242
12.3 Initialization and Configuration........................................................................................................... 242
12.4 Register Map ..................................................................................................................................... 243
12.5 Register Descriptions......................................................................................................................... 244
13. Synchronous Serial Interface (SSI) ................................................................................. 274
13.1 Block Diagram ................................................................................................................................... 274
13.2 Functional Description ....................................................................................................................... 275
13.2.1 Bit Rate Generation ........................................................................................................................... 275
13.2.2 FIFO Operation .................................................................................................................................. 275
13.2.3 Interrupts............................................................................................................................................ 275
13.2.4 Frame Formats .................................................................................................................................. 276
13.3 Initialization and Configuration........................................................................................................... 283
13.4 Register Map ..................................................................................................................................... 284
13.5 Register Descriptions......................................................................................................................... 285
14. Analog Comparator........................................................................................................... 309
14.1 Block Diagram ................................................................................................................................... 309
14.2 Functional Description ....................................................................................................................... 309
14.2.1 Internal Reference Programming....................................................................................................... 310
14.3 Initialization and Configuration........................................................................................................... 311
May 4, 2007
5
Preliminary
Share Link: 