LM3S817-IQN50-A0T 查看數據表（PDF） - Unspecified

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LM3S817-IQN50-A0T

Microcontroller

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List of Figures

List of Figures

Figure 1-1. Stellaris® High-Level Block Diagram ...................................................................................... 26

Figure 1-2. LM3S817 Controller System-Level Block Diagram ................................................................... 32

Figure 2-1. CPU Block Diagram .................................................................................................................. 34

Figure 2-2. TPIU Block Diagram .................................................................................................................. 35

Figure 5-1. JTAG Module Block Diagram .................................................................................................... 47

Figure 5-2. Test Access Port State Machine ............................................................................................... 50

Figure 5-3. IDCODE Register Format.......................................................................................................... 54

Figure 5-4. BYPASS Register Format ......................................................................................................... 54

Figure 5-5. Boundary Scan Register Format ............................................................................................... 55

Figure 6-1. External Circuitry to Extend Reset............................................................................................. 57

Figure 6-2. Main Clock Tree ........................................................................................................................ 60

Figure 7-1. Flash Block Diagram ................................................................................................................. 98

Figure 8-1. GPIO Module Block Diagram .................................................................................................. 116

Figure 8-2. GPIO Port Block Diagram........................................................................................................ 117

Figure 8-3. GPIODATA Write Example...................................................................................................... 118

Figure 8-4. GPIODATA Read Example ..................................................................................................... 118

Figure 9-1. GPTM Module Block Diagram ................................................................................................. 154

Figure 9-2. 16-Bit Input Edge Count Mode Example ................................................................................. 158

Figure 9-3. 16-Bit Input Edge Time Mode Example................................................................................... 159

Figure 9-4. 16-Bit PWM Mode Example .................................................................................................... 160

Figure 10-1. WDT Module Block Diagram ................................................................................................... 185

Figure 11-1. ADC Module Block Diagram.................................................................................................... 209

Figure 11-2. Internal Temperature Sensor Characteristic............................................................................ 211

Figure 12-1. UART Module Block Diagram.................................................................................................. 239

Figure 12-2. UART Character Frame........................................................................................................... 240

Figure 13-1. SSI Module Block Diagram...................................................................................................... 274

Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer).......................................................... 276

Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 277

Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 278

Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 278

Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 279

Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 279

Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 280

Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 280

Figure 13-10. MICROWIRE Frame Format (Single Frame)........................................................................... 281

Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 282

Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 283

Figure 14-1. Analog Comparator Module Block Diagram ............................................................................ 309

Figure 14-2. Structure of Comparator Unit................................................................................................... 310

Figure 14-3. Comparator Internal Reference Structure ............................................................................... 311

Figure 15-1. PWM Module Block Diagram................................................................................................... 320

Figure 15-2. PWM Count-Down Mode......................................................................................................... 321

Figure 15-3. PWM Count-Up/Down Mode ................................................................................................... 321

Figure 15-4. PWM Generation Example In Count-Up/Down Mode ............................................................. 322

Figure 15-5. PWM Dead-Band Generator ................................................................................................... 322

Figure 16-1. Pin Connection Diagram ....................................................................................................... 349

8

May 4, 2007

Preliminary

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