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LP62S4096E-T 查看數據表(PDF) - AMIC Technology

零件编号
产品描述 (功能)
生产厂家
LP62S4096E-T
AMICC
AMIC Technology AMICC
LP62S4096E-T Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LP62S4096E-T Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V
n Access times: 55ns / 70ns (max.)
n Current:
Very low power version: Operating: 30mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 32-pin TSOP/TSSOP 36-ball CSP package
Product Family
General Description
The LP62S4096E-T is a low operating current 4,194,304-bit
static random access memory organized as 524,288 words
by 8 bits and operates on a low power supply range: 2.7V to
3.3V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Data retention is guaranteed at a power supply voltage as low
as 2V.
n CE2 pin for CSP package only
Product Family
Operating
Temperature
VCC
Range
Speed
Power Dissipation
Data Retention Standby Operating
(ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.)
LP62S4096E-T -25°C ~ +85°C 2.7V~3.6V 55ns / 70ns
0.08µA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
0.3µA
5mA
Package
Type
32L TSOP
32L TSSOP
36B CSP
Pin Configurations
n TSOP/(TSSOP)
n CSP (Chip Size Package)
36-pin Top View
16
1
17
32
1
A A0
B I/O5
2
3
4
A1 CE2 A3
A2 WE A4
5
6
A6 A8
A7 I/O1
C I/O6
NC A5
I/O2
D GND
VCC
E VCC
GND
F I/O7
A18 A17
I/O3
G I/O8 OE CE1 A16 A15 I/O4
H A9 A10 A11 A12 A13 A14
Pin No.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Pin
Name
A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4
Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin
Name
A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE
(January, 2002, Version 2.0)
AMIC Technology, Inc.

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