LP62S4096EV-55LLT 查看數據表（PDF） - AMIC Technology

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LP62S4096EV-55LLT

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

LP62S4096E-T Series

AC Characteristics (continued)

Symbol

Parameter

LP62S4096E-55LLT LP62S4096E-70LLT Unit

Min.

Max.

Min.

Max.

Write Cycle

tWC

Write Cycle Time

55

-

70

-

ns

tCW1

Chip Enable to End of Write

50

-

60

-

ns

tAS

Address Setup Time

0

-

0

-

ns

tAW

Address Valid to End of Write

50

-

60

-

ns

tWP

Write Pulse Width

40

-

50

-

ns

tWR

Write Recovery Time

0

-

0

-

ns

tWHZ

Write to Output in High Z

0

25

0

25

ns

tDW

Data to Write Time Overlap

25

-

30

-

ns

tDH

Data Hold from Write Time

0

-

0

-

ns

tOW

Output Active from End of Write

5

-

5

-

ns

Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are

not referred to output voltage levels.

Timing Waveforms Read Cycle 1(1)

tRC

Address

tAA

OE

CE1

tOE

tOH

tOLZ5

CE2

DOUT

tACE1 , tACE2

tCLZ1 , tCLZ2

tOHZ5

tCHZ1 , tCHZ2

(January, 2002, Version 2.0)

6

AMIC Technology, Inc.

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