LPC2101 查看數據表（PDF） - Philips Electronics
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LPC2101 Datasheet PDF : 32 Pages
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Philips Semiconductors
LPC2101/2102/2103
Single-chip 16-bit/32-bit microcontrollers
Table 3: Pin description …continued
Symbol
LQFP48
PLCC44
P0.21/SSEL1/ 3 [4]
9 [4]
MAT3.0
P0.22/AD0.0 32 [4]
P0.23/AD0.1 33 [1]
P0.24/AD0.2 34 [1]
P0.25/AD0.6 38 [1]
P0.26/AD0.7 39 [1]
P0.27/TRST/ 8 [4]
CAP2.0
P0.28/TMS/
9 [4]
CAP2.1
P0.29/TCK/
CAP2.2
10 [4]
P0.30/TDI/
MAT3.3
15 [4]
P0.31/TDO
RTXC1
RTXC2
RTCK
16 [4]
20 [5]
25 [5]
26 [5]
X1
11
X2
12
DBGSEL
27
RST
6
35 [4]
36 [1]
37 [1]
41 [1]
n.c.
13 [4]
14 [4]
15 [4]
20 [4]
21 [4]
24 [5]
29 [5]
n.c.
16
17
30
11
VSS
7, 19, 43
LPC2101_02_03_1
Preliminary data sheet
1, 12, 23
Type
I/O
I
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I
O
O
O
I
O
I/O
I
O
I
I
I
Description
P0.21 — General purpose Input/output digital pin (GPIO).
SSEL1 — Slave Select for SPI1. Selects the SPI interface as
a slave.
MAT3.0 — PWM output for Timer 3, channel 0.
P0.22 — General purpose Input/output digital pin (GPIO).
AD0.0 — ADC 0, input 0.
P0.23 — General purpose Input/output digital pin (GPIO).
AD0.1 — ADC 0, input 1.
P0.24 — General purpose Input/output digital pin (GPIO).
AD0.2 — ADC 0, input 2.
P0.25 — General purpose Input/output digital pin (GPIO).
AD0.6 — ADC 0, input 6.
P0.26 — General purpose Input/output digital pin (GPIO).
AD0.7 — ADC 0, input 7.
P0.27 — General purpose Input/output digital pin (GPIO).
TRST — Test Reset for JTAG interface.
CAP2.0 — Capture input for Timer 2, channel 0.
P0.28 — General purpose Input/output digital pin (GPIO).
TMS — Test Mode Select for JTAG interface.
CAP2.1 — Capture input for Timer 2, channel 1.
P0.29 — General purpose Input/output digital pin (GPIO).
TCK — Test Clock for JTAG interface.
CAP2.2 — Capture input for Timer 2, channel 2.
P0.30 — General purpose Input/output digital pin (GPIO).
TDI — Test Data In for JTAG interface.
MAT3.3 — PWM output 3 for Timer 3.
P0.31 — General purpose output only digital pin (GPIO).
TDO — Test Data Out for JTAG interface.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Returned test clock output: Extra signal added to the JTAG
port. Assists debugger synchronization when processor
frequency varies. Bidirectional pin with internal pull-up.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Debug select: When LOW, the part operates normally. When
HIGH, debug mode is entered. Input with internal pull-down.
External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
Ground: 0 V reference.
Rev. 01 — 18 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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