LQFP208 查看數據表（PDF） - NXP Semiconductors.

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LQFP208

32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller

NXP Semiconductors. 

NXP Semiconductors

5. Block diagram

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

SWD/TRACE PORT/JTAG

HIGH-SPEED PHY

LPC1850/30/20/10

TEST/DEBUG

INTERFACE

ARM

CORTEX-M3

DMA

ETHERNET(1)

10/100

MAC

IEEE 1588

HIGH-

SPEED

USB0(1)

HOST/

DEVICE/

OTG

USB1(1)

HOST/

DEVICE

LCD(1)

SD/

MMC

AHB MULTILAYER MATRIX

masters

slaves

BRIDGE 0

BRIDGE 1

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

MOTOR

CONTROL

PWM(1)

I2C0

I2S0

I2S1

C_CAN1

SCU

GPIO

interrupts

GPIO GROUP0

interrupt

GPIO GROUP1

interrupt

BRIDGE 2

RI TIMER

USART2

USART3

TIMER2

TIMER3

SSP1

QEI(1)

GIMA

BRIDGE 3

I2C1

10-bit DAC

C_CAN0

10-bit ADC0

10-bit ADC1

BRIDGE

CGU

CCU1

CCU2

RGU

slaves

BRIDGE

ALARM TIMER

BACKUP REGISTERS

POWER MODE CONTROL

CONFIGURATION

REGISTERS

EVENT ROUTER

OTP MEMORY

RTC

RTC OSC

12 MHz IRC

SPIFI

EMC

64 kB ROM

64/96 kB LOCAL SRAM

40 kB LOCAL SRAM

16/32 kB AHB SRAM

16 kB +

16 kB AHB SRAM(1)

HS GPIO

SCT

RTC POWER DOMAIN

= connected to GPDMA

(1) Not available on all parts (see Table 2).

Fig 1. LPC1850/30/20/10 block diagram

002aaf218

LPC1850_30_20_10

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.1 — 7 February 2013

© NXP B.V. 2013. All rights reserved.

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