LS7060C-S 查看數據表（PDF） - LSI Corporation

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LS7060C-S

32 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS

LSI Corporation  

SCAN RESET

ENABLE

SCAN

ST1 (int.)

ST2 (int.)

ST3 (int.)

ST4 (int.)

ST5 (int.)

tRSCPW

tRSCR

t t SCPW SCPW

ENABLE (int.)

CASCADE ENABLE

DATA OUTPUTS

tDCE

tDOE

valid

LSB

tDOD

valid

LSB+1

valid

LSB +2

tDCE

valid

MSB

FIGURE 3A. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM FOR LS7060C

SCAN RESET

tRSCPW

ENABLE

SCAN

tRSCR

t t SCPW

SCPW

ST1 (int.)

ST2 (int.)

ST3 (int.)

ST4 (int.)

ST5 (int.)

ST6 (int.)

ENABLE (int.)

CASCADE ENABLE

DATA OUTPUTS

tDCE

tDOE

valid

LSB

tDOD

valid

LSB+1

valid

LSB +2

valid

LSB+3

tDCE

valid

MSB

FIGURE 3B. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM FOR LS7061C.

7060C/62C-121801-4

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