LS7211N 查看數據表（PDF） - LSI Corporation

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LS7211N

PROGRAMMABLE DIGITAL DELAY TIMER

LSI Corporation  

ƒi

+V

ƒo

1

A

2B

+V

3

V DD

4

CLOCK

LS7212N

7

RESET

18

TRIG

9

OUT

Vss

8

17

WB0

16

WB1

15

WB2

14

WB3

13

WB4

12

WB5

11

WB6

10

WB7

CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1

In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can

be obtained according to the equation:

ƒo =

ƒi

W+2

where W (weighting factor) = 0 to 255

The ƒo pulse width is non-symmetrical (non-50% duty -cycle)

CASE 2. MODE = DD; PRESCALE FACTOR, S = 1

In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can

be obtained according to the equation:

ƒo =

ƒi

2 (W + 1)

where W (weighting factor) = 0 to 255

The ƒo pulse widths are symmetrical with 50% duty -cycle

EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2

ƒi

ƒo

Case 1, Mode = DO; ÷4

ƒo

Case 2, Mode = DD; ÷ 6

7211N-052606-8

FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER

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