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LT1910IS8-PBF

Protected High Side MOSFET Driver

Linear Technology 

LT1910

Applications Information

to the supply at the same point as the positive end of the

sense resistor.

The drain-sense threshold voltage has a positive tempera-

ture coefficient, allowing PTC sense resistors to be used

(see Printed Circuit Board Shunts). The selection of RS

should be based on the minimum threshold voltage:

RS = 50mV/ISET

Thus the 0.02Ω drain-sense resistor in Figure 3 will yield

a minimum trip current of 2.5A. This simple configuration

is appropriate for resistive or inductive loads that do not

generate large current transients at turn-on.

Automatic Restart Period

The timing capacitor, CT , shown in Figure 3 determines

the length of time the power MOSFET is held off follow-

ing a current limit trip. Curves are given in the Typical

Performance Characteristics to show the restart period

for various values of CT . For example, CT = 0.33µF yields

a 50ms restart period.

Defeating Automatic Restart

Some applications are required to remain off after a fault

occurs. When the LT1910 is being driven from CMOS logic,

this can be easily implemented by connecting resistor R2

between the IN and TIMER pins as shown in Figure 4. R2

supplies the sustaining current for an internal SCR which

latches the TIMER pin LOW under a fault condition. The

FAULT pin is set active LOW when the TIMER pin falls below

3.3V. This keeps the MOSFET gate from turning on and the

5V

FAULT OUTPUT

5V ON = 5V

CMOS

LOGIC OFF = 0V

R2

2k

R1

5.1k

3 FAULT

4 IN LT1910

2 TIMER

GND

CT

1

1µF

1910 F04

Figure 4. Latch-Off Configuration (Autorestart Defeated)

FAULT pin from resetting HIGH until the IN pin has been

recycled. CT is used to prevent the FAULT pin from glitch-

ing whenever the IN pin recycles to turn on the MOSFET

unsuccessfully under an existing fault condition.

Inductive vs Capacitive Loads

Turning on an inductive load produces a relatively benign

ramp in MOSFET current. However, when an inductive

load is turned off, the current stored in the inductor needs

somewhere to decay. A clamp diode connected directly

across each inductive load normally serves this purpose.

If a diode is not employed, the LT1910 clamps the MOSFET

gate 0.7V below ground. This causes the MOSFET to resume

conduction during the current decay with (V+ + VGS + 0.7V)

across it, resulting in high dissipation peaks.

Capacitive loads exhibit the opposite behavior. Any load

that includes a decoupling capacitor will generate a current

equal to CLOAD • (∂V/∂t) during capacitor in-rush. With

large electrolytic capacitors, the resulting current spike

can play havoc with the power supply and false trip the

current-sense comparator.

Turn-on ∂V/∂t is controlled by the addition of the simple

network shown in Figure 5. This network takes advantage of

the fact that the MOSFET acts as a source follower during

turn-on. Thus the ∂V/∂t on the source can be controlled

by controlling the ∂V/∂t on the gate.

V+ 8

6

SENSE

LT1910

5

GATE

GND

1 C2 +

50µF

50V

CURRENT LIMIT

DELAY NETWORK

1N4148

CD

RD (≤10k)

∂V/∂t CONTROL NETWORK

1N4148

R1

R2

100k 100k

C1

24V

RS

0.01Ω

Q1

IRFZ34

15V

1N4744

+

CLOAD

1910 F05

Figure 5. Control and Current Limit Delay

1910fb

8

For more information www.linear.com/LT1910

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