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3433EFE

High Voltage Step-Up/Step-Down DC/DC Converter

Linear Technology 

LT3433

PI FU CTIO S

VFB (Pin 7): Error Amplifier Inverting Input. The noninvert-

ing input of the error amplifier is connected to an internal

1.231V reference. The VFB pin is connected to a resistor

divider from the converter output. Values for the resistor

connected from VOUT to VFB (RFB1) and the resistor con-

nected from VFB to ground (RFB2) can be calculated to pro-

gram converter output voltage (VOUT) via the following

relation:

VOUT = 1.231 • (RFB1 + RFB2)/RFB2

The VFB pin input bias current is 35nA, so use of extremely

high value feedback resistors could cause a converter

output that is slightly higher than expected. Bias current

error at the output can be estimated as:

∆VOUT(BIAS) = 35nA • RFB1

The voltage on VFB also controls the LT3433 oscillator

frequency through a “frequency-foldback” function. When

the VFB pin voltage is below 0.8V, the oscillator runs slower

than the 200kHz typical operating frequency. The oscilla-

tor frequency slows with reduced voltage on the pin, down

to 50kHz when VFB = 0V.

The VFB pin voltage also controls switch current limit

through a “current-limit foldback” function. At VFB = 0V, the

maximum switch current is reduced to half of the normal

value. The current limit value increases linearly until VFB

reaches 0.6V when the normal maximum switch current

level is restored. The frequency and current-limit foldback

functions add robustness to short-circuit protection and

help prevent inductor current runaway during start-up.

SS (Pin 10): Soft Start. Connect a capacitor (CSS) from this

pin to ground. The output voltage of the LT3433 error

amplifier corresponds to the peak current sense amplifier

output detected before resetting the switch output(s). The

soft-start circuit forces the error amplifier output to a zero

peak current for start-up. A 5µA current is forced from the

SS pin onto an external capacitor. As the SS pin voltage

ramps up, so does the LT3433 internally sensed peak cur-

rent limit. This forces the converter output current to ramp

from zero until normal output regulation is achieved. This

function reduces output overshoot on converter start-up.

The time from VSS = 0V to maximum available current can

be calculated given a capacitor CSS as:

tSS = (2.7 • 105)CSS or 0.27s/µF

SHDN (Pin 11): Shutdown. If the SHDN pin is externally

pulled below 0.5V, low current shutdown mode is initiated.

During shutdown mode, all internal functions are disabled,

and ICC is reduced to 10µA. This pin is intended to receive

a digital input, however, there is a small amount of input

hysteresis built into the SHDN circuit to help assure glitch-

free mode switching. If shutdown is not desired, connect

the SHDN pin to VIN.

VBIAS (Pin 12): Internal Local Supply. Much of the LT3433

circuitry is powered from this supply, which is internally

regulated to 2.5V through an on-board linear regulator.

Current drive for this regulator is sourced from the VIN pin.

The VBIAS supply is short-circuit protected to 5mA.

The VBIAS supply only sources current, so forcing this pin

above the regulated voltage allows the use of external power

for much of the LT3433 circuitry. When using external drive,

this pin should be driven above 3V to assure the internal

supply is completely disabled. This pin is typically diode-

connected to the converter output to maximize conversion

efficiency. This pin must be bypassed with at least a 0.1µF

ceramic capacitor to SGND.

VOUT (Pin 13): Converter Output Pin. This pin voltage is

compared with the voltage on VIN internally to control

operation in single or 2-switch mode. When the ratios of

the two voltages are such that a >75% duty cycle is required

for regulation, the low side switch is enabled. Drive bias for

the low side switch is also derived directly from this pin.

PWRGND (Pin 14): High Current Ground Reference. This

is the current return for the low side switch and corresponds

to the emitter of the low side switch transistor.

SW_L (Pin 15): Ground Referenced Switch Output. This pin

is the collector of the low side switch transistor. The low

side switch shorts the SW_L pin to PWRGND when enabled.

The series impedance of the ground-referenced switch is

0.6Ω.

Exposed Pad (Pin 17): Exposed Pad must be soldered to

PCB ground for optimal thermal performance.

3433f

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