LT3572E 查看數據表（PDF） - Linear Technology

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LT3572E

Dual Full-Bridge Piezo Driver with 900mA Boost Converter

Linear Technology 

LT3572

APPLICATIONS INFORMATION

Duty Cycle

The typical maximum duty cycle of the LT3572 is 95% at

1MHz. This maximum duty cycle reduces as the switch-

ing frequency is increased. The duty cycle for a given

application is given by:

DC = VOUT + VD – VIN

VOUT + VD – VCESAT

where VD is the diode forward drop, typically 0.5V and

VCESAT is, in the worst case, 310mV at 0.8A. The LT3572

can be used at higher duty cycles, but must be operated

in the discontinuous mode so that the actual duty cycle

is reduced.

FB Resistor Network

The output voltage is programmed with a resistor divider

between the output and the FB pin. Choose the resistors

according to:

R1=

R2

⎛

⎝⎜

VOUT

1.225V

–

1⎞⎠⎟

Shutdown Pins

When held below 0.3V, SHDNA and SHDNB prevent the

drivers from switching and keep the outputs in a high

impedance state. If SHDN is held below 0.3V then the

switching regulator is prevented from turning on. When

any one of these pins are pulled above 1.5V the internal

circuitry is turned on and the respective output is allowed

to operate. When the LT3572 is not in use all three pins

should be pulled low.

Oscillator

The LT3572 can operate at switching frequencies from

500kHz up to 2.25MHz by changing the value of the re-

sistor R3 on the RT pin. Figure 2 shows a graph of RT vs

Switching Frequency.

The oscillator can be synchronized with an external clock

applied to the SYNC pin. When synchronizing the oscilla-

tor, the free running frequency must be set approximately

10000

1000

100

10

RT RESISTANCE (kΩ)

100

3572 F02

Figure 2. RT Resistance vs Switching Frequency

15% lower than the desired synchronized frequency. If

the sync function is not used the SYNC pin must be tied

to ground.

PGOOD

The part has a power good feature that detects when the

output boost converter is up and in regulation. When the

part is turned off or not in regulation the PGOOD pin is

in a high impedance state. When the part is within 95%

of regulation the PGOOD pin is pulled low signaling that

the output is valid. If the output then falls below 85% of

regulation the PGOOD pin is put back in a high impedance

state. Whenever the output is not in regulation the output

pins in the driver aren’t allowed to switch and are placed

in a high impedance state. The PGOOD pin is an open

drain of an NMOS devices with an impedance of 1kΩ and

should be tied to VIN through a resistor.

Soft-Start

The soft-start feature limits the inrush current drawn from

the supply upon start-up. An internal current source with a

nominal 4.5μA current source charges an external capacitor

C2. The voltage on the soft-start pin is used to control the

output of the error amplifier, which limits the maximum

peak current through the inductor and the inrush current

drawn from the supply during start-up.

3572fa

8

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