LT3959EUHE 查看數據表（PDF） - Linear Technology

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LT3959EUHE

Wide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch

Linear Technology 

LT3959

Pin Functions

DRIVE: DRIVE LDO Supply Pin. This pin can be connected

to either VIN or a quasi-regulated voltage supply such as a

DC converter output. This pin must be bypassed to GND

with a minimum of 1µF capacitor placed close to the pin.

Tie this pin to VIN if not used.

EN/UVLO: Shutdown and Undervoltage Detect Pin. An

accurate 1.22V (nominal) falling threshold with externally

programmable hysteresis detects when power is okay to

enable switching. Rising hysteresis is generated by the

external resistor divider and an accurate internal 2.2μA

pull-down current. An undervoltage condition resets soft-

start. Tie to 0.4V, or less, to disable the device and reduce

VIN quiescent current below 1μA.

FBX: Voltage Regulation Feedback Pin for Positive or

Negative Outputs. Connect this pin to a resistor divider

between the output and SGND. FBX is the input of two error

amplifiers—one configured to regulate a positive output;

the other, a negative output. Depending upon topology

selected, switching causes the output to ramp positive or

negative. The appropriate amplifier takes control while the

other becomes inactive. Additionally FBX is input for two

window comparators that indicate through the PGOOD

pin when the output is within 5% of the regulation volt-

ages. FBX also modulates the switching frequency during

start-up and fault conditions when FBX is close to SGND.

GND: Source Terminal of Switch and the GND Input to the

Switch Current Comparator.

GNDK: Kelvin Connection Pin between GND and SGND.

Kelvin connect this pin to the SGND plane close to the IC.

See the Board Layout section.

INTVCC: Regulated Supply for Internal Loads and Gate

Driver. Regulated to 4.75V if powered from DRIVE or

regulated to 3.75V if powered from VIN. The INTVCC pin

must be bypassed to SGND with a minimum of 4.7µF

capacitor placed close to the pin.

NC: No Internal Connection. Leave these pins open or

connect them to the adjacent pins.

PGOOD: Output Ready Status Pin. An open-collector pull

down on PGOOD asserts when INTVCC is greater than

2.7V and the FBX voltage is within 5% (80mV if VFBX =

1.6V or 40mV if VFBX = –0.8V) of the regulation voltage.

RT: SwitchingFrequencyAdjustmentPin.Setthefrequency

using a resistor to SGND. Do not leave the RT pin open.

SGND: Signal Ground. Must be soldered directly to the

signal ground plane. Connect to ground terminal of: ex-

ternal resistor dividers for FBX and EN/UVLO; capacitors

for INTVCC, SS, and VC; and resistor RT.

SS: Soft-Start Pin. This pin modulates compensation pin

voltage (VC) clamp. The soft-start interval is set with an

external capacitor. The pin has a 10µA (typical) pull-up

current source to an internal 2.5V rail. The soft-start pin

is reset to SGND by an EN/UVLO undervoltage condition,

an INTVCC undervoltage condition or an internal thermal

lockout.

SW: Drain of Internal Power N-Channel MOSFET.

SYNC: Frequency Synchronization Pin. Used to synchronize

the internal oscillator to an outside clock. If this feature is

used, an RT resistor should be chosen to program a switch-

ing frequency 20% slower than SYNC pulse frequency.

Tie the SYNC pin to SGND if this feature is not used. This

signal is ignored during FB frequency foldback or when

INTVCC is less than 2.7V.

VIN: Supply Pin for Internal Leads and the VIN LDO Regu-

lator of INTVCC. Must be locally bypassed to GND with a

minimum of 1µF capacitor placed close to this pin.

VC: Error Amplifier Compensation Pin. Used to stabilize

the voltage loop with an external RC network. Place com-

pensation components between the VC pin and SGND.

For more information www.linear.com/LT3959

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