LTC1290C 查看數據表（PDF） - Linear Technology

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LTC1290C

Single Chip 12-Bit Data Acquisition System

Linear Technology 

LTC1290

DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which

apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL

VIH

VIL

IIH

IIL

VOH

PARAMETER

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

High Level Output Voltage

VOL

Low Level Output Voltage

IOZ

High-Z Output Leakage

ISOURCE

ISINK

ICC

Output Source Current

Output Sink Current

Positive Supply Current

CONDITIONS

VCC = 5.25V

VCC = 4.75V

VIN = VCC

VIN = 0V

VCC = 4.75V

IO = 10µA

IO = 360µA

VCC = 4.75V

IO = 1.6mA

VOUT = VCC, CS High

VOUT = 0V, CS High

VOUT = 0V

VOUT = VCC

CS High

CS High

LTC1290BC, LTC1290CC

Power Shutdown LTC1290DC, LTC1290BI

ACLK Off

LTC1290CI, LTC1290DI

LTC1290B/LTC1290C/LTC1290D

MIN TYP MAX

●

2.0

●

0.8

●

2.5

●

– 2.5

4.7

●

2.4 4.0

●

0.4

●

3

●

–3

– 20

20

●

6 12

●

5 10

UNITS

V

V

µA

µA

V

V

V

µA

µA

mA

mA

mA

µA

LTC1290BM, LTC1290CM ●

LTC1290DM

(OBSOLETE)

5 15

µA

IREF

Reference Current

I–

Negative Supply Current

VREF = 5V

CS High

●

10 50

µA

●

1 50

µA

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND, AGND

and REF– wired together (unless otherwise noted).

Note 3: VCC = 5V, VREF+ = 5V, VREF – = 0V, V – = 0V for unipolar mode and

– 5V for bipolar mode, ACLK = 4.0MHz unless otherwise specified.

Note 4: These specs apply for both unipolar and bipolar modes. In bipolar

mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096.

For example, when VREF = 5V, 1LSB (bipolar) = 2(5V)/4096 = 2.44mV.

Note 5: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6: Recommended operating conditions.

Note 7: Two on-chip diodes are tied to each reference and analog input

which will conduct for reference or analog input voltages one diode drop

below V – or one diode drop above VCC. Be careful during testing at low

VCC levels (4.5V), as high level reference or analog inputs (5V) can cause

this input diode to conduct, especially at elevated temperatures and cause

errors for inputs near full scale. This spec allows 50mV forward bias of

either diode. This means that as long as the reference or analog input does

not exceed the supply voltage by more than 50mV, the output code will be

correct. To achieve an absolute 0V to 5V input voltage range will therefore

require a minimum supply voltage of 4.950V over initial tolerance,

temperature variations and loading.

Note 8: Channel leakage current is measured after the channel selection.

Note 9: To minimize errors caused by noise at the chip select input, the

internal circuitry waits for two ACLK falling edge after a chip select falling

edge is detected before responding to control input signals. Therefore, no

attempt should be made to clock an address in or data out until the

minimum chip select setup time has elapsed.

Note 10: Increased leakage currents at elevated temperatures cause the

S/H to droop, therefore it's recommended that fACLK ≥ 125kHz at 85°C and

fACLK ≥ 15kHz at 25°C.

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5

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