LTC1472CS 查看數據表（PDF） - Linear Technology
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LTC1472CS Datasheet PDF : 16 Pages
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LTC1472
ELECTRICAL CHARACTERISTICS
(VPP Switch Section) The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VDD = 5V, VCC(IN) = 5V, VPPIN = 12V, VCCEN0 = VCCEN1 = 0V, (Note 2) unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VCC(IN)
VPPIN
VDD
ICCIN
VCC Input Voltage Range
VPP Input Voltage Range
Logic Supply Voltage Range
VCC(IN) Supply Current, No Load
(Note 7)
(Note 8)
Program to VPPIN or VCC(IN) VPPIN = 12V
Program to 0V or Hi-Z
●3
5.5
V
●0
12.6
V
● 4.5
5.5
V
●
35 60
µA
●
0.01 10
µA
IPPIN
VPPIN Supply Current, No Load
Program to VPPIN or VCC(IN)
Program to 0V or Hi-Z
●
40 80
µA
●
0.01 10
µA
IDD
VDD Supply Current, No Load
Program to VPPIN
Program to VCC(IN), VPPIN = 0V
Program to VCC(IN), VPPIN = 12V
Program to 0V or Hi-Z
●
70 120
µA
●
85 150
µA
●
40 80
µA
●
0.01 10
µA
IVPPOUT
RON
VPPENH
VPPENL
IVPPEN
VSDH
VSDL
ILIMVCC
ILIMVPP
tVPP1
tVPP2
tVPP3
tVPP4
tVPP5
tVPP6
tVPP7
tVPP8
Hi-Z Output Leakage Current
On Resistance VPPOUT to VPPIN
On Resistance VPPOUT to VCC(IN)
On Resistance VPPOUT to GND
VPP Enable Input High Voltage
VPP Enable Input Low Voltage
VPP Enable Input Current
SHDN Output High Voltage
SHDN Output Low Voltage
VPPOUT Current Limit, VCC(IN)
VPPOUT Current Limit, VPPIN
Delay and Rise Time
Delay and Rise Time
Delay and Rise Time
Delay and Fall Time
Delay and Fall Time
Delay and Fall Time
Output Turn-On Delay
Output Turn-On Delay
Program to Hi-Z, 0V < VPPOUT < 12V
VPPIN = 12V, ILOAD = 120mA
VCC(IN) = 5V, ILOAD = 5mA
VDD = 5V, ISINK = 1mA
VDD = 5V
VDD = 5V
0V < VPP EN < VDD
Program to 0V, VCC(IN) or Hi-Z, ILOAD = 400µA
Program to VPPIN, ISINK = 400µA
Program to VCC(IN), VPPOUT = 0V (Note 5)
Program to VPPIN, VPPOUT = 0V (Note 5)
From 0V to VCC(IN),VPPIN = 0V (Note 9)
From 0V to VPPIN (Note 9)
From VCC(IN) to VPPIN (Note 9)
From VPPIN to VCC(IN) (Note 10)
From VPPIN to 0V (Note 11)
From VCC(IN) to 0V, VPPIN = 0V (Note 11)
From Hi-Z to VCC(IN) (Note 9)
From Hi-Z to VPPIN (Note 9)
●
0.01 10
µA
0.50 1
Ω
1.70 5
Ω
100 250
Ω
●2
V
●
0.8
V
●
±1
µA
● 3.5
V
●
0.4
V
60
mA
100
mA
5
15
50
µs
25 85 250
µs
30 100 300
µs
5
15
50
µs
10 35 100
µs
10 30 100
µs
5
15
50
µs
25 85 250
µs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: VENH = 5V, VENL = 0V. See VCC and VPP Switch Truth Tables for
programming enable inputs for desired output states.
Note 3: Power for the VCC input logic and charge pump circuitry is derived
from the 5VIN power supply which must be continuously powered. 12V
and 3.3V power is not required to control the NMOS VCC switches. (See
Applications Information.)
Note 4: The two 3VIN supply input pins (14 and 15) must be connected
together and the two VCC(OUT) output pins (1 and 16) must be connected
together. The 3VIN supply pins do not need to be continuously powered
and may drop to 0V when not required.
Note 5: The VCC and VPP output are protected with foldback current limit
which reduces the short-circuit (0V) currents below peak permissible
current levels at higher output voltages.
Note 6: To 90% of final value.
Note 7: 12V power is only required when VPPOUT is programmed to 12V.
The external 12V regulator can be shutdown at all other times. Built-in
charge pumps power the internal NMOS switches from the 5V VDD supply
when 12V is not present.
Note 8: Power for the VPP input logic and charge pump circuitry is derived
from the VDD power supply which must be continuously powered.
Note 9: To 90% of the final value, COUT = 0.1µF, ROUT = 2.9k.
Note 10: To 10% of the final value, COUT = 0.1µF, ROUT = 2.9k.
Note 11: To 50% of the initial value, COUT = 0.1µF, ROUT = 2.9k.
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