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LTC1609I 查看數據表(PDF) - Linear Technology

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LTC1609I Datasheet PDF : 24 Pages
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LTC1609
W
FUNCTIONAL BLOCK DIAGRA
20k
R1IN
10k
R2IN
20k
5k
R3IN
4k
REF
2.5V REF
CAP
(2.5V)
AGND1
AGND2
DGND
REF BUF
INTERNAL
CLOCK
CSAMPLE
CSAMPLE
ZEROING SWITCHES
VANA
VDIG
16-BIT CAPACITIVE DAC
+
COMP
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
CS
R/C
PWRD BUSY
SERIAL INTERFACE
DATA
DATACLK
SYNC
SB/BTC EXT/INT
1609 BD
TAG
APPLICATIO S I FOR ATIO
Conversion Details
The LTC1609 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit serial output. The ADC is complete
with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs. (Please refer to the Digital Interface section for
timing information.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
8
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches CSAMPLE to ground,
injecting the analog input charge onto the summing junc-
tion. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
RIN1
VIN
RIN2
SAMPLE CSAMPLE
HOLD
CDAC
DAC
VDAC
SAMPLE
SI
+
COMPARATOR
S
A
R
16-BIT
SHIFT REGISTER
1609 F01
Figure 1. LTC1609 Simplified Equivalent Circuit
1609fa

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