LTC1520CS 查看數據表（PDF） - Linear Technology

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LTC1520CS

50Mbps Precision Quad Line Receiver

Linear Technology 

LTC1520

APPLICATIONS INFORMATION

LTC1520 receiving differential data from a PECL driver. As

in the single-ended configurations, care must be taken to

properly terminate the differential data lines to avoid

unwanted reflections, etc.

5V

3.3k

0.01µF 3.3k

5V

100Ω

5V

100-FT TWISTED PAIR

+

5V

100Ω

*

100Ω

RT

120Ω

1/4 LTC1520

–

100Ω

*MC10116

1520 F08

Figure 8. Differential Transmission Over Long Distances

0.01µF

+

1/4 LTC1520

–

+

1/4 LTC1520

–

1/4 LTC1520

+

1/4 LTC1520

–

+

1/4 LTC1520

–

9.3MHz

OSCILLATOR

WITH BETTER

THAN 45/55

DUTY CYCLE

TYPICAL STABILITY

± 5% OVER TEMPERATURE

+

1/4 LTC1520

–

6.9MHz

OSCILLATOR

OUTPUT

Alternate Uses

The tightly controlled propagation delay of the LTC1520

allows the part to serve as a fixed delay element. Figure 9

shows the LTC1520 used as a tapped delay line with 18ns

±3ns steps. Several LTC1520s may be connected in series

to form longer delay lines. Each tap in the delay line is

accurate to within ±17% over temperature.

As shown in Figure 10, the LTC1520 can be used to create

a temperature stable ring oscillator with period incre-

ments of 36ns. Low skew and good channel-to-channel

matching enable this oscillator to achieve better than a 45/

55 duty cycle (the duty cycle approaches 50/50 as more

LTC1520s are used for lower frequencies). Note that the

fixed voltage bias may either be created externally with a

resistor divider or generated internally using a bypass

capacitor and the internal open circuit bias point (approxi-

mately 3.3V). The use of the internal bias point will result

in a 1% to 2% distortion of the duty cycle.

1/4 LTC1520

1520 F10

Figure 10. Temperature Stable Ring Oscillators

Layout Considerations

A ground plane is recommended when using a high

frequency device like the LTC1520. A 0.1µF ceramic by-

pass capacitor less than 1/4 inch away from the VDD pin is

also recommended. Good bypassing is especially needed

when all four channels are driven simultaneously by the

same input. Under these conditions, and with a bypass

capacitor more than 1 1/4 inches away from the VDD pin,

the parasitic inductances will cause ringing in the VDD and

output pins. This in turn can cause false triggering of the

output short-circuit detector (Figure 11). When the by-

pass capacitor is placed close to the VDD pin, however, the

LTC1520 operates normally (Figure 12).

INPUT

5V

3.3k

0.01µF 3.3k

0ns DELAY

+

1/4 LTC1520

–

18ns DELAY

+

1/4 LTC1520

–

36ns DELAY

+

1/4 LTC1520

–

54ns DELAY

+

1/4 LTC1520

–

Figure 9. Tapped Delay Line with 18ns Steps

72ns DELAY

1520 F09

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

7

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