LTC1702AIGN 查看數據表（PDF） - Linear Technology

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LTC1702AIGN

Dual 550kHz Synchronous 2-Phase Switching Regulator Controller

Linear Technology 

LTC1702A

APPLICATIONS INFORMATION

Feedback Amplifier

Each side of the LTC1702A senses the output voltage at

VOUT with an internal feedback op amp (see Block Dia-

gram). This is a real op amp with a low impedance output,

85dB open-loop gain and 25MHz gain-bandwidth product.

The positive input is connected internally to an 800mV

reference, while the negative input is connected to the FB

pin. The output is connected to COMP, which is in turn

connected to the soft-start circuitry and from there to the

PWM generator.

Unlike many regulators that use a resistor divider con-

nected to a high impedance feedback input, the LTC1702A

is designed to use an inverting summing amplifier topol-

ogy with the FB pin configured as a virtual ground. This

allows flexibility in choosing pole and zero locations not

available with simple gm configurations. In particular, it

allows the use of “type 3” compensation, which provides

a phase boost at the LC pole frequency and significantly

improves loop phase margin (see Figure 3). The Feedback

Loop/Compensation section contains a detailed explana-

tion of type 3 feedback loops.

PGOOD Flags

PGOOD is an open-drain output, allowing it to be wire-

ORed with other open-drain/open-collector signals. An

external pull-up resistor is required for PGOOD to swing

high. Any time the FB pin is more than 5% below the

programmed value for more than 100µs, PGOOD will pull

low, indicating that the output is out of regulation. PGOOD

remains active during soft-start and current limit. The

100µs delay ensures that short output transient glitches

that are successfully “caught” by the PGOOD comparator

don’t cause momentary glitches at the PGOOD pin.

When either side of the LTC1702A is in shutdown, its

associated PGOOD pin will go high. This behavior allows

a valid PGOOD reading when the two PGOOD pins are tied

together, even if one side is shut down. It also reduces

quiescent current by eliminating the excess current drawn

by the pull-up at the PGOOD pin. As soon as the RUN/SS

pin rises above the shutdown threshold and the side

comes out of shutdown, the PGOOD pin will pull low until

the output voltage is valid. If both sides are shut down at

the same time, both PGOOD pins will go high. To avoid

confusion, if either side of the LTC1702A is shut down, the

host system should ignore the associated PGOOD pin.

0.8V

COMP

FB

FB

C2

R2

C1

C3

R3

R1

RB

VOUT

1702A F03

Figure 3. “Type 3” Feedback Loop

1702afa

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