LTC1751 查看數據表（PDF） - Linear Technology

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LTC1751

Micropower, Regulated Charge Pump DC/DC Converters

Linear Technology 

LTC1751/LTC1751-3.3/LTC1751-5

APPLICATIO S I FOR ATIO

There are several ways to reduce output voltage ripple.

For applications requiring VIN to exceed 3.3V or for

applications requiring < 100mV of peak-to-peak ripple, a

larger COUT capacitor (22µF or greater) is recommended.

A larger capacitor will reduce both the low and high

frequency ripple due to the lower charging and discharg-

ing slew rates as well as the lower ESR typically found

with higher value (larger case size) capacitors. A low ESR

ceramic output capacitor will minimize the high fre-

quency ripple, but will not reduce the low frequency

ripple unless a high capacitance value is used. An R-C

filter may also be used to reduce high frequency voltages

spikes (see Figure 1).

VOUT

LTC1751-X

+

1Ω

+

10µF

VOUT

5V

10µF

TANT

TANT

1751 F01

Figure 1. Output Ripple Reduction Technique

Note that when using a larger output capacitor the mini-

mum turn-on time of the device will increase.

Soft-Start

The LTC1751 family has built-in soft-start circuitry to

prevent excessive current flow at VIN during start-up. The

soft-start time is programmed by the value of the capacitor

at the SS pin. Typically a 2µA current is forced out of SS

causing a ramp voltage on the SS pin. The regulation loop

follows this ramp voltage until the output reaches the

correct regulation level. SS is automatically pulled to

ground whenever SHDN is low. The typical rise time is

given by the expression:

tr = 0.6ms/nF • CSS

For example, with a 4.7nF capacitor the 10% to 90% rise

time will be approximately 2.8ms. If the output charge

storage capacitor is 10µF, then the average output current

for an LTC1751-5 will be 4V/2.8ms • 10µF or 14mA, giving

28mA at the VIN pin.

The soft-start feature is optional. If there is no capacitor

on SS, the output voltage of the LTC1751 will ramp up as

quickly as possible. The start-up time will depend on

various parameters such as temperature, output loading,

charge pump and flying capacitor values and input

voltage.

PGOOD and Undervoltage Detection

The PGOOD pin on the LTC1751-3.3/LTC1751-5 performs

two functions. On start-up, it indicates when the output

has reached its final regulation level. After start-up, it

indicates when a fault condition, such as excessive load-

ing, has pulled the output out of regulation.

Once the LTC1751-3.3/LTC1751-5 are enabled via the

SHDN pin, VOUT ramps to its final regulation value slowly

by following the SS pin. The PGOOD pin switches from low

impedance to high impedance after VOUT reaches its

regulation value. If VOUT is subsequently pulled below its

correct regulation level, the PGOOD pin pulls low again

indicating that a fault exists. Alternatively, if there is a short

circuit on VOUT preventing it from ever reaching its correct

regulation level, the PGOOD pin will remain low. The lower

fault threshold, UVL, is preprogrammed to recognize

errors of – 7% below nominal VOUT. The upper fault

threshold, UVH, is preprogrammed at – 4.5% below nomi-

nal. Figure 2 shows an example of the PGOOD pin with a

normal start-up followed by an undervoltage fault.

Using an external pull-up resistor, the PGOOD pin can be

pulled high from any available voltage supply, including

the LTC1751-3.3/LTC1751-5 VOUT pin.

If PGOOD is not used it may be connected to GND.

SHDN

PGOOD

90%

VOUT

tr

UVL

UVH

10%

TIME

17515 F02

Figure 2. PGOOD During Start-Up and Undervoltage

9

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