LTC1700_ 查看數據表（PDF） - Linear Technology

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LTC1700_

High Input Voltage, Current Mode Boost, Flyback and SEPIC Controller

Linear Technology 

LTC1871-7

APPLICATIO S I FOR ATIO

Sense Resistor Selection

During the switch on-time, the control circuit limits the

maximum voltage drop across the sense resistor to about

150mV (at low duty cycle). The peak inductor current is

therefore limited to 150mV/RSENSE. The relationship be-

tween the maximum load current, duty cycle and the sense

resistor RSENSE is:

RSENSE

≤

VSENSE(MAX)

•

1– DMAX

1+

χ

2



•

IO(MAX)

The VSENSE(MAX) term is typically 150mV at low duty cycle,

and is reduced to about 100mV at a duty cycle of 92% due

to slope compensation, as shown in Figure 11.

It is worth noting that the 1 – DMAX relationship between

IO(MAX) and RSENSE can cause boost converters with a

wide input range to experience a dramatic range of maxi-

mum input and output current. This should be taken into

consideration in applications where it is important to limit

the maximum current drawn from the input supply.

200

150

100

50

0

0

0.2 0.4 0.5 0.8 1.0

DUTY CYCLE

18717 F11

Figure 11. Maximum SENSE Threshold Votlage vs Duty Cycle

Boost Converter: Power MOSFET Selection

Important parameters for the power MOSFET include the

drain-to-source breakdown voltage (BVDSS), the thresh-

old voltage (VGS(TH)), the on-resistance (RDS(ON)) versus

gate-to-source voltage, the gate-to-source and gate-to-

drain charges (QGS and QGD, respectively), the maximum

drain current (ID(MAX)) and the MOSFET’s thermal resis-

tances (RTH(JC) and RTH(JA)).

The gate drive voltage is set by the 7V INTVCC low drop

regulator. Consequently, 6V rated MOSFETs are required

in most high voltage LTC1871-7 applications.

Pay close attention to the BVDSS specifications for the

MOSFETs relative to the maximum actual switch voltage in

the application. The switch node can ring during the turn-

off of the MOSFET due to layout parasitics. Check the

switching waveforms of the MOSFET directly across the

drain and source terminals using the actual PC board lay-

out (not just on a lab breadboard!) for excessive ringing.

Calculating Power MOSFET Switching and Conduction

Losses and Junction Temperatures

In order to calculate the junction temperature of the power

MOSFET, the power dissipated by the device must be

known. This power dissipation is a function of the duty

cycle, the load current and the junction temperature itself

(due to the positive temperature coefficient of its RDS(ON)).

As a result, some iterative calculation is normally required

to determine a reasonably accurate value. Care should be

taken to ensure that the converter is capable of delivering

the required load current over all operating conditions

(line voltage and temperature), and for the worst-case

specifications for VSENSE(MAX) and the RDS(ON) of the

MOSFET listed in the manufacturer’s data sheet.

The power dissipated by the MOSFET in a boost converter

is:

PFET

=

 IO(MAX)  2

 1– D 

•

RDS(ON)

•D

•

ρT

( ) +k

•

VO2

• IO(MAX)

1– D

• CRSS

•

f

The first term in the equation above represents the I2R

losses in the device, and the second term, the switching

losses. The constant, k = 1.7, is an empirical factor

inversely related to the gate drive current and has the

dimension of 1/current. The ρT term accounts for the

temperature coefficient of the RDS(ON) of the MOSFET,

which is typically 0.4%/°C. Figure 12 illustrates the varia-

tion of normalized RDS(ON) over temperature for a typical

power MOSFET.

18717f

15

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