LTC2234I 查看數據表（PDF） - Linear Technology

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LTC2234I

10-Bit, 135Msps ADC

Linear Technology 

LTC2234

W

FUNCTIONAL BLOCK DIAGRA

AIN+

INPUT

AIN–

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

VCM

2.2µF

1.6V

REFERENCE

RANGE

SELECT

REF

SENSE

BUF

SHIFT REGISTER

AND CORRECTION

REFH

REFL INTERNAL CLOCK SIGNALS

DIFFERENTIAL

DIFF

INPUT

CONTROL

REF

LOW JITTER

LOGIC

AMP

CLOCK

DRIVER

REFLB REFHA REFLA REFHB

2.2µF

ENC+ ENC–

M0DE SHDN

OE

0.1µF

0.1µF

1µF

1µF

Figure 1. Functional Block Diagram

OUTPUT

DRIVERS

OVDD

OF

D9

•

•

•

D0

CL0CKOUT

OGND

2234 F01

2234fa

10

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