LTC2234I 查看數據表（PDF） - Linear Technology

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LTC2234I

10-Bit, 135Msps ADC

Linear Technology 

LTC2234

PI FU CTIO S

AIN+ (Pin 1): Positive Differential Analog Input.

AIN– (Pin 2): Negative Differential Analog Input.

REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins

5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with

a 2.2µF ceramic capacitor and to ground with a 1µF

ceramic capacitor.

REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 5,

6 with 0.1µF ceramic chip capacitor. Do not connect to

Pins 9, 10.

REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins

9, 10 with 0.1µF ceramic chip capacitor. Do not connect to

Pins 3, 4.

REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins

7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a

2.2µF ceramic capacitor and to ground with a 1µF ceramic

capacitor.

VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to

GND with 0.1µF ceramic chip capacitors. Adjacent pins

can share a bypass capacitor.

GND (Pins 13, 15, 45, 48): ADC Power Ground.

ENC+ (Pin 16): Encode Input. The input is sampled on the

positive edge.

ENC– (Pin 17): Encode Complement Input. The input is

sampled on the negative edge. Bypass to ground with

0.1µF ceramic for single-ended ENCODE signal.

SHDN (Pin 18): Shutdown Mode Selection Pin. Connect-

ing SHDN to GND and OE to GND results in normal

operation with the outputs enabled. Connecting SHDN to

GND and OE to VDD results in normal operation with the

outputs at high impedance. Connecting SHDN to VDD and

OE to GND results in nap mode with the outputs at high

impedance. Connecting SHDN to VDD and OE to VDD

results in sleep mode with the outputs at high impedance.

OE (Pin 19): Output Enable Pin. Refer to SHDN pin

function.

CLOCKOUT (Pin 20): Data Valid Output. Latch data on the

falling edge of CLOCKOUT.

NC (Pins 21, 24): Do not connect these pins.

D0 – D9 (Pins 25, 26, 29, 30, 31, 34, 35, 36, 39, 40):

Digital Outputs. D9 is the MSB.

OGND (Pins 22, 27, 32, 38): Output Driver Ground.

OVDD (Pins 23, 28, 33, 37): Positive Supply for the

Output Drivers. Bypass to ground with 0.1µF ceramic chip

capacitors.

OF (Pin 41): Over/Under Flow Output. High when an over

or under flow has occurred.

MODE (Pin 42): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and turns the clock duty cycle

stabilizer off. Connecting MODE to 1/3 VDD selects offset

binary output format and turns the clock duty cycle stabi-

lizer on. Connecting MODE to 2/3 VDD selects 2’s comple-

ment output format and turns the clock duty cycle stabi-

lizer on. Connecting MODE to VDD selects 2’s complement

output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 43): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 44): 1.6V Output and Input Common Mode Bias.

Bypass to ground with 2.2µF ceramic chip capacitor.

Exposed Pad (Pin 49): ADC Power Ground. The exposed

pad on the bottom of the package needs to be soldered to

ground.

2234fa

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