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LTC2240-12(RevB) 查看數據表(PDF) - Linear Technology

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LTC2240-12
(Rev.:RevB)
Linear
Linear Technology Linear
LTC2240-12 Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LTC2240-12
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
LOGIC OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load
VOS
Output Common Mode Voltage
100Ω Differential Load
l 247
350
454
mV
l 1.125 1.250 1.375
V
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD
Analog Supply Voltage
PSLEEP
Sleep Mode Power
PNAP
Nap Mode Power
LVDS OUTPUT MOD
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
l 2.375 2.5 2.625
V
1
mW
28
mW
OVDD
Output Supply Voltag
IVDD
Analog Supply Current
IOVDD
Output Supply Current
PDISS
Power Dissipation
CMOS OUTPUT MODE
(Note 8)
l 2.375 2.5 2.625
V
l
170
185
mA
l
58
70
mA
l
570
638
mW
OVDD
IVDD
PDISS
Output Supply Voltage
Analog Supply Current
Power Dissipation
(Note 8)
(Note 7)
l 0.5
2.5 2.625
V
l
170
185
mA
445
mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS
Sampling Frequency
(Note 8)
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
1
170
MHz
l 2.79 2.94 500
ns
l 1.5
2.94
500
ns
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l 2.79 2.94 500
ns
l 1.5
2.94
500
ns
tAP
Sample-and-Hold Aperture Delay
tOE
Output Enable Delay
(Note 7)
0.4
ns
l
5
10
ns
LVDS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
tC
ENC to CLKOUT Delay
(Note 7)
DATA to CLKOUT Skew
(tC – tD) (Note 7)
Rise Time
l
1
1.7
2.8
ns
l
1
1.7
2.8
ns
l –0.6
0
0.6
ns
0.5
ns
Fall Time
0.5
ns
Pipeline Latency
5
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
tC
ENC to CLKOUT Delay
(Note 7)
(Note 7)
l
1
1.7
2.8
ns
l
1
1.7
2.8
ns
224012fb
5

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