LTC1750 查看數據表（PDF） - Linear Technology

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LTC1750

14-Bit, 125/105Msps Low Power 3V ADCs

Linear Technology 

W

FUNCTIONAL BLOCK DIAGRA

LTC2255/LTC2254

AIN+

INPUT

AIN–

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

VCM

2.2µF

1.5V

REFERENCE

RANGE

SELECT

REF

SENSE

BUF

SHIFT REGISTER

AND CORRECTION

REFH

REFL INTERNAL CLOCK SIGNALS

DIFF

CLOCK/DUTY

CONTROL

REF

CYCLE

LOGIC

AMP

CONTROL

REFH 0.1µF REFL

2.2µF

1µF

1µF

CLK

M0DE SHDN

OE

Figure 1. Functional Block Diagram

OUTPUT

DRIVERS

OVDD

OF

D13

•

•

•

D0

OGND

22554 BD01

WU

W

TI I G DIAGRA

ANALOG

INPUT

CLK

D0-D13, OF

tAP

N

tH

N+1

tL

Timing Diagram

N+2

N+3

N+4

N+5

tD

N–5

N–4

N–3

N–2

N–1

N

22554 TD01

22554fa

11

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