LTC2624 查看數據表（PDF） - Linear Technology

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LTC2624

Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP

Linear Technology 

LTC2604/LTC2614/LTC2624

BLOCK DIAGRAM

GND

1

REF LO

2

REF A

3

VOUTA

4

DAC A

VOUTB

5

REF B

6

CS/LD

7

SCK

8

DAC B

CONTROL

LOGIC

DECODE

32-BIT SHIFT REGISTER

DAC D

VCC

16

REF D

15

VOUT D

14

DAC C

VOUT C

13

REF C

12

CLR

11

SDO

10

SDI

9

2604 BD

TIMING DIAGRAM

t1

t2

SCK

1

SDI

t5

t7

CS/LD

SDO

t3

t4

2

3

t8

Figure 1

t6

23

24

t10

2604 F01

OPERATION

Power-On Reset

The LTC2604/LTC2614/LTC2624 clear the outputs to

zero scale when power is first applied, making system

initialization consistent and repeatable. The LTC2604-1/

LTC2614-1/LTC2624-1 set the voltage outputs to midscale

when power is first applied.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

10

outputs from the DAC during this time. The LTC2604/

LTC2614/LTC2624 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground (typ) during power-on. See Power-On Reset Glitch

in the Typical Performance Characteristics section.

2604fd

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