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2910I

Octal Positive/Negative Voltage Monitor

Linear Technology 

LTC2910

APPLICATIONS INFORMATION

the desired delay time as a function of the value of the

timer capacitor. The TMR pin must have a minimum of

10pF or be tied to VCC. For long timeout periods, the only

limitation is the availability of a large value capacitor with

low leakage. Capacitor leakage current must not exceed

the minimum TMR charging current of 1.3µA. Tying the

TMR pin to VCC bypasses the timeout period.

Undervoltage Lockout

When VCC falls below 2V, the LTC2910 asserts an

undervoltage lockout (UVLO) condition. During UVLO,R⎯ S⎯ T⎯

is asserted and pulled low and RST is pulled high. When

VCC rises above 2V, RST and ⎯R⎯S⎯T follow the same timing

procedure as an undervoltage condition on any input.

Shunt Regulator

The LTC2910 has an internal shunt regulator. The VCC pin

operates as a direct supply input for voltages up to 6V.

In this range, the quiescent current of the device remains

below a maximum of 100µA. For VCC voltages higher than

6V, the pin functions as a shunt regulator and must have a

resistance RZ between the supply and the VCC pin to limit

the current to no greater than 10mA.

When selecting this resistance value, choose an appropriate

location on the I-V curve shown in the Typical Performance

Characteristics to accommodate any variations in VCC due

to changes in current through RZ.

RST/⎯R⎯S⎯T Output Characteristics

The DC characteristics of the RST and ⎯R⎯S⎯T pull-up and

pull-down strength are shown in the Typical Performance

Characteristics. Each has a weak internal pull-up to VCC and

a strong pull-down to ground. This arrangement allows

each pin to have open-drain behavior while possessing

several other beneficial characteristics. The weak pull-up

eliminates the need for an external pull-up resistor when

the rise time on this pin is not critical. On the other hand,

the open drain configuration allows for wired-OR connec-

tions and is useful when more than one signal needs to

pull down on the RST or ⎯R⎯S⎯T lines. VCC of 1V guarantees

a maximum VOL = 0.15V.

At VCC = 1V, the weak pull-up current on RST is barely

turned on. Therefore, an external pull-up resistor of no more

than 100k is recommended on the RST pin if the state and

pull-up strength of the RST pin is crucial at very low VCC.

Note however, by adding an external pull-up resistor, the

pull-up strength on the RST pin is increased. Therefore,

if it is connected in a wired-OR connection, the pull-down

strength of any single device must accommodate this ad-

ditional pull-up strength.

Output Rise and Fall Time Estimation

The RST and ⎯R⎯S⎯T outputs have strong pull-down capabil-

ity. The following formula estimates the output fall time

(90% to 10%) for a particular external load capacitance

(CLOAD):

tFALL ≈ 2.2 • RPD • CLOAD

where RPD is the on-resistance of the internal pull-down

transistor, typically 50Ω at VCC > 1V, and at room tem-

perature (25°C). CLOAD is the external load capacitance

on the pin. Assuming a 150pF load capacitance, the fall

time is 16.5ns.

The rise time on the RST and ⎯R⎯S⎯T pins is limited by a

400k internal pull-up resistance to VCC. A similar formula

estimates the output rise time (10% to 90%) at the RST

and ⎯R⎯S⎯T pins:

tRISE ≈ 2.2 • RPU • CLOAD

where RPU is the pull-up resistance.

Disable

The LTC2910 allows disabling the RST and ⎯R⎯S⎯T outputs

via the DIS pin. Pulling DIS high forces both outputs to

remain unasserted, regardless of any faults that occur

on the inputs. However, if a UVLO condition occurs, ⎯R⎯S⎯T

asserts and pulls low, RST asserts and pulls high, but the

timeout function is bypassed. R⎯ S⎯ T⎯ pulls high and RST pulls

low as soon as the UVLO condition is cleared.

DIS has a weak 2µA (typical) internal pull-down current

guaranteeing normal operation with the pin left open.

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