LTC3719EG 查看數據表（PDF） - Linear Technology
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LTC3719EG Datasheet PDF : 32 Pages
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LTC3719
ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VBIAS = 5V, VRUN/SS = 5V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
IQ
IRUN/SS
VRUN/SS
VRUN/SSLO
ISCL
ISDLHO
ISENSE
DFMAX
TG1, 2 tr
TG1, 2 tf
BG1, 2 tr
BG1, 2 tf
TG/BG t1D
Input DC Supply Current
Normal Mode
Shutdown
Soft-Start Charge Current
RUN/SS Pin ON Threshold
RUN/SS Pin Latchoff Arming
RUN/SS Discharge Current
Shutdown Latch Disable Current
Total Sense Pins Source Current
Maximum Duty Factor
Top Gate Transition Time:
Rise Time
Fall Time
Bottom Gate Transition Time:
Rise Time
Fall Time
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
(Note 5)
VRUN/SS = 0V
VRUN/SS = 1.9V
VRUN/SS Rising
VRUN/SS Rising from 3V
Soft Short Condition VEAIN = 0.5V, VRUN/SS = 4.5V
VEAIN = 0.5V
Each Channel: VSENSE1–, 2 – = VSENSE1+, 2+ = 0V
In Dropout
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
CLOAD = 3300pF Each Driver (Note 6)
1.2
mA
20
40
µA
– 0.5 –1.2
µA
1.0
1.5
1.9
V
4.1
4.5
V
0.5
2
4
µA
1.6
5
µA
– 85 – 60
µA
98
99.5
%
30
90
ns
40
90
ns
30
90
ns
20
90
ns
90
ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver (Note 6)
Top Switch-On Delay Time
90
ns
tON(MIN)
Minimum On-Time
Internal VCC Regulator
VINTVCC
Internal VCC Voltage
VLDO INT INTVCC Load Regulation
VLDO EXT EXTVCC Voltage Drop
VEXTVCC
EXTVCC Switchover Voltage
VLDOHYS EXTVCC Switchover Hysteresis
VID Parameters
Tested with a Square Wave (Note 7)
6V < VIN < 30V, VEXTVCC = 4V
ICC = 0 to 20mA, VEXTVCC = 4V
ICC = 20mA, VEXTVCC = 5V
ICC = 20mA, EXTVCC Ramping Positive
ICC = 20mA, EXTVCC Ramping Negative
180
ns
4.8
5.0
5.2
V
0.2
1.0
%
80
160
mV
q 4.5
4.7
V
0.2
V
VBIAS
RATTEN
Operating Supply Voltage Range
Resistance Between ATTENIN
and ATTENOUT Pins
2.7
5.5
V
10
kΩ
ATTENERR
RPULLUP
VIDTHLOW
VIDTHHIGH
VIDLEAK
VNO_CPU
Resistive Divider Error
VID0 to VID4 Pull-Up Resistance
VID0 to VID4 Logic Threshold Low
VID0 to VID4 Logic Threshold High
VID0 to VID4 Leakage
NO_CPU Maximum Output Voltage
(Note 8)
VBIAS < VID0–VID4 < 7V
INO_CPU = 2mA
q – 0.35
0.25
%
40
kΩ
0.4
V
1.6
V
±1
µA
0.4
V
sn3719 3719fs
3
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