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LTC3775EUD 查看數據表(PDF) - Linear Technology

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LTC3775EUD Datasheet PDF : 34 Pages
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LTC3775
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Oscillator
fOSC
fHIGH
fLOW
fSYNC
tON(MIN)
tOFF(MIN)
DCMAX
VMODE
VMODE(HYST)
RMODE/SYNC
Driver
Oscillator Frequency
Maximum Oscillator Frequency
Minimum Oscillator Frequency
External Sync Frequency Range
TG Minimum On-Time
TG Minimum Off-Time
Maximum TG Duty Cycle
MODE/SYNC Threshold
MODE/SYNC Hysteresis
MODE/SYNC Input Resistance to SGND
RSET = 39.2k
l 425
500
575
kHz
l 1000
kHz
l
250
kHz
With Reference to Free Running
–20
20
%
(Notes 6, 8) VMODE/SYNC = 0V
(Note 6)
30
ns
300
ns
fOSC = 500kHz
l 90
%
MODE/SYNC Rising
1.2
V
430
mV
50
BG RUP
TG RUP
BG RDOWN
TG RDOWN
BG, TG t2D
Bottom Gate (BG) Pull-Up On-Resistance
Top Gate (TG) Pull-Up On-Resistance
Bottom Gate (BG) Pull-Down On-Resistance
Top Gate (TG) Pull-Down On-Resistance
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CL = 3300pF (Note 7)
2.5
Ω
2.5
Ω
1.0
Ω
1.5
Ω
15
ns
TG, BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CL = 3300pF (Note 7)
15
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3775 is tested under pulsed load conditions such that TJ ≈ TA.
The LTC3775E is guaranteed to meet specifications from 0°C to 85°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3775I is guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD θJA), where θJA (in °C/W) is the package thermal
impedance.
Note 3: Failure to solder the exposed pad of the UD package to the PC
board will result in a thermal resistance much higher than 68°C/W.
Note 4: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 5: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
Note 6: Guaranteed by design, not subject to test.
Note 7: Rise and fall times are measured using 10% and 90% levels. Delay
and nonoverlap times are measured using 50% levels.
Note 8: The LTC3775 leading edge modulation architecture does not have
a minimum TG pulse width requirement. The TG minimum pulse width is
limited by the SW node rise and fall times.
3775fa
4

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