LTC3776EUF(RevA) 查看數據表（PDF） - Linear Technology

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LTC3776EUF
(Rev.:RevA)

Dual 2-Phase, No RSENSE™, Synchronous Controller for DDR/QDR Memory Termination

Linear Technology 

LTC3776

TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.

Shutdown Quiescent Current

vs Input Voltage

20

RUN/SS = 0V

18

16

14

12

10

8

6

4

2

0

2 3 4 5 6 7 8 9 10

INPUT VOLTAGE (V)

3736 G17

RUN/SS Start-Up Current

vs Input Voltage

0.9

RUN/SS = 0V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2345678

INPUT VOLTAGE (V)

9 10

3736 G18

PI FU CTIO S (UF/GN Package)

ITH1/ITH2 (Pins 1, 8/ Pins 4, 11): Current Threshold and

Error Amplifier Compensation Point. Nominal operating

range on these pins is from 0.7V to 2V. The voltage on

these pins determines the threshold of the main current

comparator.

PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.

When synchronizing to an external clock, this pin serves

as the lowpass filter point for the phase-locked loop. Nor-

mally a series RC is connected between this pin and ground.

When SYNC/SSEN is tied to GND, this pin serves as the fre-

quency select input. Tying this pin to GND selects 300kHz

operation; tying this pin to VIN selects 750kHz operation.

Floating this pin selects 550kHz operation. When SYNC/

SSEN is tied to VIN to enable spread spectrum operation,

a capacitor (1nF to 4.7nF) should be connected from this

pin to SGND to filter and smooth the changes in frequency

of the LTC3776’s internal oscillator.

SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves

as the ground connection for most internal circuits.

VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin

powers the entire chip except for the gate drivers. Externally

filtering this pin with a lowpass RC network (e.g.,

R = 10Ω, C = 1μF) is suggested to minimize noise pickup,

especially in high load current applications.

VREF (Pin 6/Pin 9): Reference voltage input for channel 2.

6

The positive input of the error amplifier for channel 2 senses

one half of the voltage on this pin through an internal

resistor divider.

PGOOD (Pin 9/Pin 12): Power Good Output Voltage Moni-

tor Open-Drain Logic Output. This pin is pulled to ground

when the voltage on either feedback pin (VFB1, VFB2) is not

within ±13.3% of its nominal set point.

PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power

Ground. These pins serve as the ground connection for the

gate drivers and the negative input to the reverse current

comparators. The Exposed Pad (UF package) must be

soldered to PCB ground.

RUN/SS (Pin 14/Pin 17): Run Control Input and Optional

External Soft-Start Input. Forcing this pin below 0.65V shuts

down the chip (both channels). Driving this pin to VIN or

releasing this pin enables the chip, using the chip’s inter-

nal soft-start. An external soft-start can be programmed by

connecting a capacitor between this pin and ground.

TG1/TG2 (Pins 17, 15/Pins 20, 18): Top(PMOS)GateDrive

Output. These pins drive the gates of the external P-channel

MOSFETs. These pins have an output swing from PGND to

SENSE+.

SYNC/SSEN (Pin 18/Pin 21): Synchronization Input and

Spread Spectrum Modulation Enable Input. To synchronize

the LTC3776’s switching frequency to an external clock

3776fa

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