LTC3776EUF 查看數據表（PDF） - Linear Technology

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产品描述 (功能)

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LTC3776EUF

Dual 2-Phase, No RSENSE™, Synchronous Controller for DDR/QDR Memory Termination

Linear Technology 

W

FU CTIO AL DIAGRA (Controller 2)

LTC3776

CLK2

RS2

SQ

R

OV2

SC2

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

ICMP

SLOPE2

SW2

SENSE2+

SENSE2+

VIN

TG2

PGND

SW2

ANTISHOOT

THROUGH

SENSE2+ BG2

PGND

MP2

L2

COUT2

MN2

VOUT2

SHDN

EAMP

VFB2

40k

VREF

40k

120k

40k

ITH2

VFB2

OV2

OVP

VREF/8

SC2

SCP

1.1 • VREF/2

VFB2/2

SHORT1

RITH2

CITH2

3776 CONT2

U

OPERATIO (Refer to Functional Diagram)

Main Control Loop

The LTC3776 uses a constant frequency, current mode

architecture with the two controllers operating 180 de-

grees out of phase. During normal operation, the top

external P-channel power MOSFET is turned on when the

clock for that channel sets the RS latch, and turned off

when the current comparator (ICMP) resets the latch. The

peak inductor current at which ICMP resets the RS latch is

determined by the voltage on the ITH pin, which is driven

by the output of the error amplifier (EAMP). The VFB pin

receives the output voltage feedback signal from an exter-

nal resistor divider. This feedback signal is compared to a

reference (either the internal 0.6V reference for controller

1 or the divided down VREF pin for CH2) by the EAMP.

3776f

9

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