LTC6943C 查看數據表（PDF） - Linear Technology

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LTC6943C

Micropower, Dual Precision Instrumentation Switched Capacitor Building Block

Linear Technology 

LTC6943

APPLICATIO S I FOR ATIO

precision DVM, the change of the voltage across CH with

respect to an input CM voltage variation. During the

sampling and holding mode, charges are being trans-

ferred and minute voltage transients will appear across the

holding capacitor. Although the RON on the switches is low

enough to allow fast settling, as the sampling frequency

increases, the rate of charge transfer increases and the

average voltage measured with a DVM across it will

increase proportionally; this causes the CMRR of the

sampled data system, as seen by a “continuous” instru-

ment (DVM), to decrease (Figure 2).

Switch Charge Injection

Figure 3 shows one out of the eight switches of the

LTC6943, configured as a basic sample-and-hold circuit.

When the switch opens, a ‘‘hold step’’ is observed and its

magnitude depends on the value of the input voltage.

Figure 4 shows charge injected into the hold capacitor. For

instance, a 2pCb of charge injected into a 0.01µF capacitor

causes a 200µV hold step. As shown in Figure 4, there is

a predictable and repeatable charge injection cancellation

when the input voltage is close to half the supply voltage

of the LTC6943. This is a unique feature of this product,

containing charge-balanced switches fabricated with a

self-aligning gate CMOS process. Any switch of the

LTC6943, when powered with symmetrical dual supplies,

will sample-and-hold small signals around ground with-

out any significant error.

140

CS = CH = 1µF

120

CS = 1µF, CH = 0.1µF

100

80

60

40

20

100

1k

10k

fOSC (Hz)

100k

6943 • AI02

Figure 2. CMRR vs Sampling Frequency

Shielding the Sampling Capacitor for Very High CMRR

Internal or external parasitic capacitors from the C+ pin(s)

to ground affect the CMRR of the LTC6943 (Figure 1).

The common mode error due to the internal junction

capacitances of the C+ Pin(s) 1 and 9 is cancelled through

internal circuitry. The C+ pin, therefore, should be used as

the top plate of the sampling capacitor. A shield placed

underneath the sampling capacitor and connected to C–

helps to boost the CMRR to 120dB (Figure 5).

Excessive external parasitic capacitance between the C–

pins and ground indirectly degrades CMRR; this becomes

visible especially when the LTC6943 is used with clock

frequencies above 2kHz. Because of this, if a shield is

used, the parasitic capacitance between the shield and

circuit ground should be minimized.

It is recommended that the outer plate of the sampling

capacitor be connected to the C– pin(s).

COSC Pin (14)

The COSC pin can be used with an external capacitor, COSC,

connected from Pin 14 to Pin 15, to modify the internal

oscillator frequency. If Pin 16 is floating, the internal 24pF

capacitor, plus any external interpin capacitance, set the

oscillator frequency around 190kHz with ±5V supply. The

typical performance characteristics curves provide the

necessary information to set the oscillator frequency for

various power supply ranges. Pin 14 can also be driven

with an external CMOS level clock to override the internal

oscillator.

1

5

1/8 LTC6943

VIN

1000pF

5V

+

1/2 LTC1013

–

–5V

VOUT

V+

SAMPLE

HOLD TO PIN 14

0V

6943 • AI03

Figure 3

6943f

6

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