LTC6945 查看數據表（PDF） - Linear Technology

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LTC6945

Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N Synthesizer

Linear Technology 

LTC6945

PIN FUNCTIONS

VREFO+ (Pin 1): 3.15V to 3.45V Positive Supply Pin for

REFO Circuitry. This pin should be bypassed directly to

the ground plane using a 0.1μF ceramic capacitor as close

to the pin as possible.

REFO (Pin 2): Reference Frequency Output. This produces

a low noise square wave, buffered from the REF± differential

inputs. The output is self-biased and must be AC-coupled

with a 22nF capacitor.

STAT (Pin 3): Status Output. This signal is a configurable

logical OR combination of the UNLOK, LOK, THI and TLO

status bits, programmable via the STATUS register. See

the Operations section for more details.

CS (Pin 4): Serial Port Chip Select. This CMOS input initi-

ates a serial port communication burst when driven low,

ending the burst when driven back high. See the Operations

section for more details.

SCLK (Pin 5): Serial Port Clock. This CMOS input clocks

serial port input data on its rising edge. See the Operations

section for more details.

SDI (Pin 6): Serial Port Data Input. The serial port uses

this CMOS input for data. See the Operations section for

more details.

SDO (Pin 7): Serial Port Data Output. This CMOS three-

state output presents data from the serial port during a

read communication burst. Optionally attach a resistor

of >200k to GND to prevent a floating output. See the

Operations section for more details.

VD+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial

Port Circuitry. This pin should be bypassed directly to the

ground plane using a 0.1μF ceramic capacitor as close to

the pin as possible.

MUTE (Pin 9): RF Mute. The CMOS active-low input mutes

the RF± differential outputs while maintaining internal bias

levels for quick response to de-assertion.

GND (Pins 10, 17, 18, 19, 20, 21): Negative Power Supply

(Ground). These pins should be tied directly to the ground

plane with multiple vias for each pin.

RF–, RF+ (Pins 11, 12): RF Output Signals. The VCO

output divider is buffered and presented differentially on

these pins. The outputs are open collector, with 136Ω

(typical) pull-up resistors tied to VRF+ to aid impedance

matching. If used single-ended, the unused output should

be terminated to 50Ω. See the Applications Information

section for more details on impedance matching.

VRF+ (Pin 13): 3.15V to 3.45V Positive Supply Pin for

RF Circuitry. This pin should be bypassed directly to the

ground plane using a 0.01μF ceramic capacitor as close

to the pin as possible.

BB (Pin 14): RF Reference Bypass. This output must be

bypassed with a 1.0μF ceramic capacitor to GND. Do not

couple this pin to any other signal.

VCO–, VCO+ (Pins 15, 16): VCO Input Signals. The dif-

ferential signal placed on these pins is buffered with a low

noise amplifier and fed to the internal output and feedback

dividers. These self-biased inputs must be AC-coupled

and present a single-ended 121Ω (typical) resistance

to aid impedance matching. They may be used single-

ended by bypassing VCO– to GND with a capacitor. See

the Applications Information section for more details on

impedance matching.

VVCO+ (Pin 22): 3.15V to 3.45V Positive Supply Pin for

VCO Circuitry. This pin should be bypassed directly to the

ground plane using a 0.01μF ceramic capacitor as close

to the pin as possible.

GND (23): Negative Power Supply (Ground). This pin is

attached directly to the die attach paddle (DAP) and should

be tied directly to the ground plane.

VCP+ (Pin 24): 3.15V to 5.25V Positive Supply Pin for Charge

Pump Circuitry. This pin should be bypassed directly to

the ground plane using a 0.1μF ceramic capacitor as close

to the pin as possible.

CP (Pin 25): Charge Pump Output. This bi-directional cur-

rent output is normally connected to the external loop filter.

See the Applications Information section for more details.

6945f

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