TC2054(2002) 查看數據表（PDF） - Microchip Technology

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TC2054
(Rev.:2002)

50 mA, 100 mA, and 150 mA CMOS LDOs with Shutdown and Error Output

Microchip Technology 

4.0 THERMAL CONSIDERATIONS

4.1 Power Dissipation

The amount of power the regulator dissipates is prima-

rily a function of input and output voltage, and output

current.

The following equation is used to calculate worst case

power dissipation:

EQUATION 4-1:

PD ≈ (VIN – VOUTMIN)ILOADMAX

Where:

PD

=

VINMAX =

VOUTMIN =

ILOADMAX =

Worst case actual power dissipation

Maximum voltage on VIN

Minimum regulator output voltage

Maximum output (load) current

The maximum allowable power dissipation (Equation

4-2) is a function of the maximum ambient temperature

(TAMAX), the maximum allowable die temperature (125

°C) and the thermal resistance from junction-to-air

(θJA). The 5-Pin SOT-23A package has a θJA of

approximately 220°C/Watt when mounted on a typical

two layer FR4 dielectric copper clad PC board.

EQUATION 4-2:

PDMAX

=

T----J---M---A--X----–-----T----A---M---A--X-

θJA

Where all terms are previously defined

TC2054/2055/2186

Equation 4-1 can be used in conjunction with Equation

4-2 to ensure regulator thermal operation is within lim-

its. For example:

Given:

VINMAX = 3.0V ±5%

VOUTMIN = 2.7V – 2.5%

ILOADMAX = 40mA

TAMAX = 55°C

Find 1. Actual power dissapation

:

2. Maximum allowable dissapation

Actual power dissipation:

PD

≈ (VINMAX – VOUTMIN)ILOADMAX

= [(3.0 x 1.05) – (2.7 x .975)]40 x 10–3

= 20.7mW

Maximum allowable power dissipation:

PDMAX

=

(---T---J---M---A--X----–----T----A---M---A--X--)-

θJA

(---1---2---5-----–-----5---5----)

220

= 318mW

In this example, the TC2054 dissipates a maximum of

only 20.7mW; far below the allowable limit of 318mW.

In a similar manner, Equation 4-1 and Equation 4-2 can

be used to calculate maximum current and/or input

voltage limits.

4.2 Layout Considerations

The primary path of heat conduction out of the package

is via the package leads. Therefore, layouts having a

ground plane, wide traces at the pads, and wide power

supply bus lines combine to lower θJA and, therefore,

increase the maximum allowable power dissipation

limit.

© 2002 Microchip Technology Inc.

DS21663B-page 5

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