L8575 查看數據表（PDF） - Agere -> LSI Corporation

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L8575

Dual-Resistive, Low-Cost Subscriber Line Interface Circuit (SLIC)

Agere -> LSI Corporation 

Advance Data Sheet

March 1997

L8575

Dual-Resistive, Low-Cost SLIC

Preliminary Pin Information (continued)

Table 1. Pin Descriptions (continued)

Pin Symbol Type

Name/Function

31 RGBNA I Battery Noise Gain Resistor (Channel A). The current flowing out of PRA is 50 times

the current flowing into RGBNA. Connect a resistor from RGBNA to AGND to set the

gain of the channel A battery noise cancellation circuit.

32 RSA

I Ring Sense (Channel A). Positive input of channel A transmit op amp. Connect one

high-value resistor between RSA and the Ring of loop A and another high-value resis-

tor between RSA and AGND.

33 TSA

I Tip Sense (Channel A). Negative input of channel A transmit op amp. Connect one

high-value resistor between TSA and the Tip of loop A and another high-value resistor

between TSA and XMTA.

34 XMTA O Transmit Signal Output (Channel A). Channel A transmit amplifier output.

35 RTNA I Ring-Trip Negative (Channel A). Negative sense input for the ring-trip detector.

36 RTPA

I Ring-Trip Positive (Channel A). Positive sense input for the ring-trip detector.

37 RDTA O Test Relay Driver (Channel A). This output drives an external test relay.

38 RDRA O Ringing Relay Driver (Channel A). This output drives the external ringing relay.

39 RDDA O Disconnect Relay Driver (Channel A). This output drives an external relay.

40 DGND — Digital Ground. Ground for channel A relay drivers.

41 VDDD — 5 V Digital dc Supply. 5 V supply for logic and relay driver flyback diodes.

42 CFLTA I/O Fault Filter (Channel A). Connect a 0.1 µF capacitor from CFLTA to AGND. This

capacitor filters Tip/Ring transients from the channel A fault detector.

43 EN

I Enable. A high-to-low transition on this logic input latches the data in the 8-bit serial

shift register into the output latches. The logic level of EN also controls which data is

shifted into the 8-bit serial shift register (refer to CLK pin description).

44 CLK

I Clock. When the enable input (EN) is high, a low-to-high transition on this logic input

shifts data at the data input pin (DI) into the 8-bit serial shift register. When the enable

input (EN) is low, a low-to-high transition latches the states of the internal detectors into

the 8-bit serial shift register.

Lucent Technologies Inc.

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