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LV8044LP 查看數據表(PDF) - SANYO -> Panasonic

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LV8044LP Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LV8044LP,LV8044LQ
Continued from preceding page.
Pin No.
37
Pin name
PI3/MO
Function
Photosensor drive output 3/position detection monitor
Equivalent circuit
17
VCC
Logic system power supply
1
PGND1
Channels 1/2/5 - Power system ground
30
PGND2
Channels 3/4/6 - Power system ground
34
SGND
Signal system ground
Serial Data Input Specifications
1. Serial Data Input Setup
First set STB low and then input the SDATA and SCLK signals. The SCLK signal is not accepted when STB is high.
SDATA inputs the data in the order D0, D1, ... D6, D7.
Data is transferred on the rising edge of SCLK and after all data has been transferred, all the data is latched on the rising
edge of STB.
2. Timing with which the Serial Data Settings are Reflected in the Output
STP timing mode (applies to microstep driver settings)
Type 1: The hold, reset, and enable settings, as well as the reference voltage setting are reflected at the same time as
the STB signal data latch operation.
Type 2: The forward/reverse (FR) and the excitation setting mode (MS) setting that are set at STP setup are reflected
in the output at the next clock rising edge after data latch.
STB timing (applies to settings other than the above)
Type 1: The PWM driver, constant-current driver, PI, and other settings are reflected at the same time as the STB signal
data latch operation.
No.A0438-8/26

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