M24256-B 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M24256-B

256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines

STMicroelectronics 

M24256-B, M24128-B

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

First byte of instruction

with RW = 0 already

decoded by M24xxx

NO ACK

Returned

YES

Next

NO

Operation is

Addressing the

Memory

ReSTART

YES

Send

Byte Address

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

AI01847

internal address counter. The counter is then in-

cremented. The master terminates the transfer

with a STOP condition, as shown in Figure 8, with-

out acknowledging the byte output.

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. The

master does acknowledge the data byte output in

this case, and the memory continues to output the

next byte in sequence. To terminate the stream of

bytes, the master must not acknowledge the last

byte output, and must generate a STOP condition.

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’

and the memory continues to output data from

memory address 00h.

Acknowledge in Read Mode

In all read modes, the memory waits, after each

byte read, for an acknowledgment during the 9th

bit time. If the master does not pull the SDA line

low during this time, the memory terminates the

data transfer and switches to its stand-by state.

8/19

Share Link: