CAT24WC33 查看數據表（PDF） - Catalyst Semiconductor => Onsemi

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CAT24WC33

32K/64K-Bit I2C Serial CMOS EEPROM

Catalyst Semiconductor => Onsemi 

CAT24WC33/65

accessed is protected from programming by the device’s READ operation. The Master device first performs a

failure to send an acknowledge after the first byte of data ‘dummy’ write operation by sending the START condi-

is received.

tion, slave address and byte addresses of the location it

wishes to read. After CAT24WC33/65 acknowledges,

READ OPERATIONS

the Master device sends the START condition and the

slave address again, this time with the R/W bit set to one.

The READ operation for the CAT24WC33/65 is initiated The CAT24WC33/65 then responds with its acknowl-

in the same manner as the write operation with one edge and sends the 8-bit byte requested. The master

exception, that R/W bit is set to one. Three different device does not send an acknowledge but will generate

READ operations are possible: Immediate/Current Ad-

dress READ, Selective/Random READ and Sequential

READ.

Immediate/Current Address Read

ts The CAT24WC33/65’s address counter contains the

address of the last byte accessed, incremented by one.

r In other words, if the last READ or WRITE access was

to address N, the READ immediately following would

a access data from address N+1. If N=E (where E=4095

for 24WC33 and E=8191 for 24WC65), then the counter

will ‘wrap around’ to address 0 and continue to clock out

P data. After the CAT24WC33/65 receives its slave ad-

dress information (with the R/W bit set to one), it issues

an acknowledge, then transmits the 8 bit byte requested.

d The master device does not send an acknowledge, but

will generate a STOP condition.

e Selective/Random Read

Selective/Random READ operations allow the Master

u device to select at random any memory location for a

a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT24WC33/65 sends the initial 8-

bit byte requested, the Master will respond with an

acknowledge which tells the device it requires more

data. The CAT24WC33/65 will continue to output an 8-

bit byte for each acknowledge sent by the Master. The

operation will terminate when the Master fails to respond

with an acknowledge, thus sending the STOP condition.

The data being transmitted from CAT24WC33/65 is

outputted sequentially with data from address N fol-

lowed by data from address N+1. The READ operation

address counter increments all of the CAT24WC33/65

address bits so that the entire memory array can be read

during one operation. If more than E (where E=4095 for

24WC33 and E=8191 for 24WC65) bytes are read out,

the counter will ‘wrap around’ and continue to clock out

data bytes.

tin Figure 8. Immediate Address Read Timing

nS

T

oBUS ACTIVITY: A

MASTER R

T

c SDA LINE S

SLAVE

ADDRESS

S

T

DATA

O

P

P

is A

N

C

O

K

A

C

DK

SCL

8

9

SDA

© 2005 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

8TH BIT

DATA OUT

NO ACK

7

STOP

24WC33/65 F10

Doc No. 1049, Rev. D

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