M41T94(2003) 查看數據表（PDF） - STMicroelectronics
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M41T94 Datasheet PDF : 31 Pages
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Table 2. Function Table
Mode
E
Disable Reset
H
WRITE
L
SCL
Input Disabled
AI04630
SDI
Input Disabled
Data Bit latch
M41T94
SDO
High Z
High Z
READ
L
X
AI04631
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 8. Data and Clock Timing
CPOL CPHA
0
0
C
Next data bit shift (1)
1
1
C
SDI
MSB
LSB
SDO
MSB
LSB
AI04632
Signal Description
Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI). The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each re-
ceived this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL). The serial clock provides the
timing for the serial interface (as shown in Figure
10, page 12 and Figure 11, page 12). The W/R Bit,
addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output
data on the SDO pin changes state after the falling
edge of the clock input.
The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2, page 7 and Figure
8, page 7).
Chip Enable (E). When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is re-
quired prior to the start of any operation.
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