M41T56M6(2006) 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M41T56M6
(Rev.:2006)

Serial real-time clock with 56 bytes NVRAM

STMicroelectronics 

Operation

2

Operation

M41T56

2.1

2.1.1

2.1.2

The M41T56 clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 64 bytes

contained in the device can then be accessed sequentially in the following order:

1. Seconds register

2. Minutes register

3. Century/hours register

4. Day register

5. Date register

6. Month register

7. Years register

8. Control register

9. RAM

The clock continually monitors VCC for an out of tolerance condition. Should VCC fall below

VPFD, the device terminates an access in progress and resets the device address counter.

Inputs to the device will not be recognized at this time to prevent erroneous data from being

written to the device from an out of tolerance system. When VCC falls below VBAT, the device

automatically switches over to the battery and powers down into an ultra low current mode

of operation to conserve battery life. Upon power-up, the device switches from battery to

VCC at VBAT and recognizes inputs when VCC goes above VPFD volts.

2-wire bus characteristics

This bus is intended for communication between different ICs. It consists of two lines: one

bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the

SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is High.

● Changes in the data line while the clock line is High will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

Bus not busy

Both data and clock lines remain High.

Start data transfer

A change in the state of the data line, from High to Low, while the clock is High, defines the

START condition.

8/28

Share Link: