IDT7MB4048S35P 查看數據表（PDF） - Integrated Device Technology
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IDT7MB4048S35P Datasheet PDF : 6 Pages
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IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
tRC
tAA
OE
tOE
CS
DATAOUT
tOLZ (5)
tACS
tCLZ (5)
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
DATAOUT
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
COMMERCIAL TEMPERATURE RANGE
tOH
tOHZ (5)
tCHZ (5)
2675 drw 06
tOH
2675 drw 07
CS
DATAOUT
tCLZ (5)
tACS
tCHZ (5)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition LOW.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
2675 drw 08
7.11
4
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