SM5838AS 查看數據表（PDF） - Nippon Precision Circuits

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SM5838AS

5120 × 8-bit Synchronous FIFO

Nippon Precision Circuits  

SM5838AS

FUNCTIONAL DESCRIPTION

At power-ON reset, device operation can become

irregular during the interval when the control circuits

are being reset. After power-ON reset is released,

this can take up to several 10s of ms in some cases.

Write Reset Cycle, Read Reset Cycle

After power-ON, the write address pointer and read

address pointer positions are undefined. Accordingly,

it is necessary to initialize the pointers using a write

reset cycle and read reset cycle, respectively.

A write reset cycle (read reset cycle) is valid when

RW (RR) goes LOW for an interval that satisfies

both the CLK rising edge setup time (tRS) and hold

time (tRH). Note that a write reset cycle (read reset

cycle) can occur simultaneously with a write cycle

(read cycle). If the cycles are not simultaneous, then

the write reset cycle (read reset cycle) is completed

at the start of the next write cycle (read cycle).

Write reset cycle

n cycle

t CKW

reset cycle

0 cycle

1 cycle

CLK

t CKW

t RS

t RW

t RH

RW

t RH

t RS

DIN (n-1) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

t DS

(n)

,,,,,,,,,,t,,,,,DH,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

t DS

(0)

,,,,,,,,,,t,,,,,DH,,,,,,,,,,,,,,,,,,,,

(1)

WE="L"

Read reset cycle

n cycle

t CKW

CLK

t CKW

t RS

RR

t RH

DOUT (n-1) ,,,,,,,,,,tA,,,,,,,,,,,,,,,,,,,,

(n)

reset cycle

t RR

,,,,,,,,,,t,,,,,A ,,,,,,,,,,,,,,,

t OH

0 cycle

t RH

t RS

(0) ,,,,,,,,,,t,,,,,A,,,,,,,,,,,,,,,,,,,,

(0)

t OH

Note the even if a reset period (tRW, tRR) is zero

length in the write reset and read reset cycles, the

reset operation does take place.

1 cycle

,,,,,,,,,,t,,,,,A,,,,,,,,,,,,,,,,,,,,

(1)

t OH

RE="L" , OE="L"

NIPPON PRECISION CIRCUITS—6

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