MT46V2M32 查看數據表（PDF） - Micron Technology

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MT46V2M32

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these ad-

ditional functions are DLL enable/disable. These func-

tions are controlled via the bits shown in Figure 3. The

extended mode register is programmed via the LOAD

MODE REGISTER command to the mode register (with

BA0 = 1 and BA1 = 0) and will retain the stored informa-

tion until it is programmed again or the device loses

power. Although not required by the Micron device,

the enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiat-

ing any subsequent operation. Violating either of these

requirements could result in unspecified operation.

Output Drive Strength

The reduced drive strength for all outputs are speci-

fied to be SSTL_2. The x32 supports an option for im-

pedance matched drive. This option is intended for

the support of the lighter load and/or point-to-point

environments. The selection of the impedance drive

strength will alter the DQs and DQSs from SSTL_2,

Class I drive strength to a reduced drive strength, which

is approximately 30 percent of the SSTL_2 Class II,

drive strength.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles must occur before a READ command

can be issued.

64Mb: x32

DDR SDRAM

BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode

11 01

Operating Mode

DS DLL Register (Ex)

E0

DLL

0

Enable

1

Disable

E1 Drive Strength

0 Impedance Match

1

Reduced

E10 E9 E8 E7 E6 E5 E4 E3 E2 E1, E0 Operating Mode

0 0 0 0 0 0 0 0 0 Valid Normal Operation

- - - - - - - - - - All other states reserved

NOTE: 1. E13 and E12 (BA0 and BA1) must be 1, 0 to select the

Extended Mode Register (vs. the base Mode Register).

Figure 3

Extended Mode Register Definition

64Mb: x32 DDR SDRAM

2M32DDR-07.p65 – Rev. 12/01

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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