MT46V2M32 查看數據表（PDF） - Micron Technology

零件编号

产品描述 (功能)

生产厂家

MT46V2M32

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 1.

Read Latency

The READ latency is the delay, in clock cycles, be-

tween the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 3 clocks, as shown in Figure 2.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. Table 2

indicates the operating frequencies at which each CAS

latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

CK#

CK

COMMAND

T0

READ

DQS

T1

NOP

CL = 2

T2 T2n T3 T3n

NOP

NOP

DQ

CK#

CK

COMMAND

T0

READ

DQS

T1

T2

NOP

NOP

CL = 3

T3 T3n

NOP

DQ

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

TRANSITIONING DATA

Figure 2

CAS Latency

DON’T CARE

64Mb: x32

DDR SDRAM

Table 2

CAS Latency

SPEED

-5

-55

-6

-65

ALLOWABLE OPERATING

FREQUENCY (MHz)

CL = 2

CL = 3

83 ≤ f ≤ 125

83 ≤ f≤ 200

83 ≤ f≤ 100

83 ≤ f≤ 183

83 ≤ f≤ 100

83 ≤ f≤ 166

83 ≤ f≤ 100

83 ≤ f≤ 150

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7-A10 each

set to zero, and bits A0-A6 set to the desired values. A

DLL reset is initiated by issuing a MODE REGISTER

SET command with bits A7, A9 - A10 each set to zero, bit

A8 set to one, and bits A0-A6 set to the desired values.

Although not required by the Micron device, JEDEC

specifications recommend when a LOAD MODE REG-

ISTER command is issued to reset the DLL, it should

always be followed by a LOAD MODE REGISTER com-

mand to select normal operating mode.

All other combinations of values for A7-A10 are re-

served for future use and/or test modes. Test modes

and reserved states should not be used because un-

known operation or incompatibility with future ver-

sions may result.

64Mb: x32 DDR SDRAM

2M32DDR-07.p65 – Rev. 12/01

9

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

Share Link: