M27V256 查看數據表（PDF） - STMicroelectronics

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M27V256

256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM

STMicroelectronics 

M27V256

Table 5. AC Measurement Conditions

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

High Speed

≤ 10ns

0 to 3V

1.5V

Standard

≤ 20ns

0.4V to 2.4V

0.8V and 2V

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

High Speed

3V

0V

1.5V

1.3V

1N914

3.3kΩ

Standard

t(s) 2.4V

Produc 0.4V

2.0V

0.8V

AI01822

DEVICE

UNDER

TEST

OUT

CL

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

AI01823B

olete Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

s Symbol

Parameter

Ob CIN

Input Capacitance

- COUT Output Capacitance

t(s) Note: 1. Sampled only, not 100% tested.

uc DEVICE OPERATION

d The modes of operation of the M27V256 are listed

ro in the Operating Modes. A single power supply is

required in the read mode. All inputs are TTL lev-

P els except for VPP and 12V on A9 for Electronic

te Signature.

le Read Mode

o The M27V256 has two control functions, both of

s which must be logically active in order to obtain

bdata at the outputs. Chip Enable (E) is the power

Ocontrol and should be used for device selection.

Test Condition

VIN = 0V

VOUT = 0V

Min

Max

Unit

6

pF

12

pF

dresses are stable, the address access time

(tAVQV) is equal to the delay from E to output

(tELQV). Data is available at the output after delay

of tGLQV from the falling edge of G, assuming that

E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

Standby Mode

The M27V256 has a standby mode which reduces

the supply current from 10mA to 10µA with low

voltage operation VCC ≤ 3.6V, see Read Mode DC

Characteristics table for details. The M27V256 is

Output Enable (G) is the output control and should placed in the standby mode by applying a CMOS

be used to gate data to the output pins, indepen- high signal to the E input. When in the standby

dent of device selection. Assuming that the ad- mode, the outputs are in a high impedance state,

independent of the G input.

4/15

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