M27V256 查看數據表（PDF） - STMicroelectronics
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M27V256 Datasheet PDF : 15 Pages
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M27V256
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70°C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = Vcc)
Symbol Alt
Parameter
Test Condition
-120
M27V256
-150
-200
Unit
Min Max Min Max Min Max
tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL
120
150
200 ns
tELQV
tCE
Chip Enable Low to Output
Valid
G = VIL
120
150
200 ns
tGLQV
tOE
Output Enable Low to Output
Valid
E = VIL
45
50
60 ns
tEHQZ (2)
tDF
Chip Enable High to Output
Hi-Z
G = VIL
0 35 0 40 0 50 ns
tGHQZ (2)
tDF
Output Enable High to Output
Hi-Z
E = VIL
0 35 0 40 0 50 ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
0
t(s) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
duc Figure 5. Read Mode AC Waveforms
Pro A0-A14
olete E
- Obs G
roduct(s) Q0-Q7
VALID
tAVQV
tGLQV
tELQV
tAXQX
VALID
tEHQZ
tGHQZ
0
ns
Hi-Z
AI00758B
lete P System Considerations
o The power switching characteristics of Advance
s CMOS EPROMs require careful decoupling of the
bdevices. The supply current, ICC, has three seg-
Oments that are of interest to the system designer:
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
the standby current level, the active current level, placed as close to the device as possible. In addi-
and transient current peaks that are produced by tion, a 4.7µF bulk electrolytic capacitor should be
the falling and rising edges of E. The magnitude of used between VCC and VSS for every eight devic-
this transient current peaks is dependent on the es. The bulk capacitor should be located near the
capacitive and inductive loading of the device at power supply connection point. The purpose of the
the output. The associated transient voltage peaks bulk capacitor is to overcome the voltage drop
can be suppressed by complying with the two line caused by the inductive effects of PCB traces.
6/15
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