M28010 查看數據表（PDF） - STMicroelectronics
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M28010 Datasheet PDF : 23 Pages
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M28010
Table 3. Operating Modes 1
Mode
E
G
Read
VIL
VIL
Write
VIL
VIH
Stand-by / Write Inhibit
VIH
X
Write Inhibit
X
X
Write Inhibit
X
VIL
Output Disable
Note: 1. X = VIH or VIL.
X
VIH
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal VCC comparator
inhibits the Write operations if the VCC voltage is
lower than VWI (see Table 4A to Table 4C). Once
the voltage applied on the VCC pin goes over the
W
DQ0-DQ7
VIH
Data Out
VIL
Data In
X
Hi-Z
VIH
Data Out or Hi-Z
X
Data Out or Hi-Z
X
Hi-Z
VWI threshold (VCC>VWI), write access to the
memory is allowed after a time-out tPUW, as
specified in Table 4A to Table 4C.
Further protection against data corruption is
offered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Table 4A. Power-Up Timing1 for M28010 (5V range)
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28010-W (3V range)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Table 4C. Power-Up Timing1 for M28010-R (2V range)
(TA = –40 to 85 °C; VCC = 1.8 to 2.4 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Min .
5
5
3.0
Max.
4.2
Unit
ms
ms
V
Min .
5
5
2.0
Max.
2.6
Unit
ms
ms
V
Min .
5
5
1.2
Max.
1.7
Unit
ms
ms
V
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