IS42S32200A-5T 查看數據表（PDF） - Integrated Silicon Solution

零件编号

产品描述 (功能)

生产厂家

IS42S32200A-5T

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

IS42S32200A

ISSI ®

FUNCTIONAL DESCRIPTION

The 64Mb SDRAMs 512K x 32 x 4 banks) are quad-bank

DRAMs which operate at 3.3V and include a synchronous

interface (all signals are registered on the positive edge of

the clock signal, CLK). Each of the 16,777,216-bit banks

is organized as 2,048 rows by 256 columns by 32bits.

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0 and BA1 select the bank, A0-A10

select the row). The address bits (A0-A7) registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.

The following sections provide detailed information covering

device initialization, register definition, command

descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner.

The 64M SDRAM is initialized after the power is applied

to VCC and VCCQ (simultaneously) and the clock is stable.

A 100µs delay is required prior to issuing any command

other than a COMMAND INHIBIT or a NOP. The COMMAND

INHIBIT or NOP may be applied during the 100us period

and continue should at least through the end of the period.

With at least one COMMAND INHIBIT or NOP command

having been applied, a PRECHARGE command should be

applied once the 100µs delay has been satisfied. All

banks must be precharged. This will leave all banks in an

idle idle state where two AUTO REFRESH cycles must be

performed. After the AUTO REFRESH cycles are complete,

the SRDRAM is then ready for mode register programming.

The mode register should be loaded prior to applying any

operational command because it will power up in an

unknown state.

Integrated Silicon Solution, Inc. — 1-800-379-4774

11

ADVANCE INFORMATION Rev. 00B

09/21/01

Share Link: