EDE5104GBSA 查看數據表（PDF） - Elpida Memory, Inc

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EDE5104GBSA

512M bits DDR-II SDRAM

Elpida Memory, Inc 

Block Diagram

CK

/CK

CKE

A0 to A13, BA0, BA1

/CS

/RAS

/CAS

/WE

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Mode

register

Row

address

buffer

and

refresh

counter

Bank 3

Bank 2

Bank 1

Memory cell array

Bank 0

Column

address

buffer

and

burst

counter

Sense amp.

Column decoder

Data control circuit

Latch circuit

CK, /CK

DLL

Input & Output buffer

DQ

DQS, /DQS

RDQS, /RDQS

ODT

DM

Preliminary Data Sheet E0249E30 (Ver. 3.0)

10

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