NT512S72V4PA0GR-8B 查看數據表（PDF） - Nanya Technology
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NT512S72V4PA0GR-8B
Nanya Technology
NT512S72V4PA0GR-8B Datasheet PDF : 12 Pages
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NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
64Mx72 bit One Bank Registered SDRAM Module
based on 64Mx4, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
Features
l JEDEC-standard 168-pin, dual in-line memory module
(DIMM)
l PC133- and PC100-compliant
l Registered inputs with one-clock delay
l Phase-lock loop (PLL) clock driver to reduce loading
l ECC-optimized pinout
l Inputs and outputs are LVTTL (3.3V) compatible
l Single 3.3V ± 0.3V Power Supply
l Fully synchronous to positive edge
l Suspend Mode and Power Down Mode
l Auto Refresh (CBR) and Self Refresh
l Automatic and controlled Precharge commands
l SDRAMs have 4 internal banks (64Mx4 SDRAM)
l Module has 1 physical bank 512MB (64 Meg x 72)
l 8192 Refresh cycles distributed across 64ms
l DIMM CAS latency * (Registered mode) :
Speed grade
Frequency
CAS latency
-7K
133MHz
3
-75B
133MHz
4
-8B
100MHz
3
* DIMM CAS latency = device CL + 1 for registered mode.
l Programmable Operation:
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, and 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect (SPD) with Write Protect
Description
The NANYA NT512S72V4PA0GR is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module (DIMM) organized as a 64Mx72
high-speed memory array. The DIMM uses eighteen 64Mx4 SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed
data-transfer rates of 100MHz and 133MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system
clock.
The DIMM is intended for use in applications operating at 100MHz and 133MHz memory bus speeds. All control and address signals are
re-driven through registers/buffers to the SDRAM devices. Operating in registered mode (REGE pin tied high), the control/address input signals
are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed
by one clock).
A phase-lock loop (PLL) on the DIMM is used to re-drive the clock signals to both the SDRAM devices and the registers to minimize system
clock loading. (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated on the DIMM). A single clock enable (CKE0) controls all
devices on the DIMM, enabling the use of SDRAM Power Down modes.
Prior to any access operation, the device CAS latency and burst type/length/operation type must be programmed into the DIMM by address
inputs A0-A12 and I/O addresses BA0 and BA1 using the mode register set cycle. The DIMM CAS latency when operated in Registered mode
is one clock later than the device CAS latency due to the address and control signals being clocked to the SDRAM devices.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data
are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by
providing a high level to pin 81 on the DIMM. An on-board pull-down resistor keeps this in the Write Enable mode.
All NANYA 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.
Ordering Information
Part Number
NT512S72V4PA0GR -7K
NT512S72V4PA0GR -75B
NT512S72V4PA0GR -8B
* CL = CAS Latency
Device Timing
MHz.
CL t RCD t RP
143MHz 3
3
3
133MHz 2
2
2
133MHz 3
3
3
100MHz 2
2
2
125MHz 3
3
3
100MHz 2
2
2
DIMM CAS latency
4
3
4
3
4
3
Organization
64Mx72
Leads
Gold
Power
3.3V
Preliminary 06 / 2001
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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